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Patent # Description
US-9,635,365 Coding unit quantization parameters in video coding
A method is provided that includes receiving a coded largest coding unit in a video decoder, wherein the coded largest coding unit includes a coded coding unit...
US-9,633,995 Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS...
A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a...
US-9,633,993 Bipolar SCR
A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second...
US-9,633,991 Mutual ballasting multi-finger bidirectional ESD device
An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a...
US-9,633,849 Implant profiling with resist
A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist...
US-9,629,294 Packaged device for detecting factory ESD events
An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device....
US-9,628,311 Sounding reference signal processing for LTE
A wireless communication receiver including a serial to parallel converter receiving an radio frequency signal, a fast Fourier transform device connected to...
US-9,628,006 Angular frequency extractor for controlling a brushed DC motor
An apparatus includes a motor driver configured to drive a motor across a pair of input terminals to the motor and a current sense unit configured to sense the...
US-9,627,334 Self-aligned under bump metal
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with...
US-9,621,145 Sense amplifier latch with offset correction
A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling...
US-9,618,959 Reference generator circuit with dynamically tracking threshold
A circuit includes a reference circuit configured to receive a reference input voltage and provides a first output signal that is a function of the reference...
US-9,615,427 Exploiting constructive interference from ambient conditions
An optical system includes an optical illumination source, an optical receiver, a correlation determination circuit, and an ambient condition control circuit....
US-9,615,386 Random access channel false alarm control
A wireless device includes a preamble detector configured to identify preambles transmitted via a random access channel of a wireless network. The preamble...
US-9,615,315 Powerline communication network system having device that performs a joining process
Disclosed embodiments include a system having one or more member devices coupled to a network and a power line communication (PLC) device. The PLC device is...
US-9,614,704 Methods and apparatus to perform serial communications
Methods and apparatus to perform serial communications are disclosed. An example serial data transmitter includes: a clock signal generator to generate a...
US-9,614,659 CTLE gear shifting to enable CDR frequency lock in wired communication
A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method...
US-9,614,584 Simultaneous launching of multiple signal channels in a dielectric waveguide using different electromagnetic modes
A device is configured for transmitting multiple channels of information through a dielectric waveguide (DWG). The device generates at least a first radio...
US-9,614,580 Network device with frequency hopping sequences for all channel-numbers for channel hopping with blacklisting
Disclosed examples include methods and network devices for communicating in a wireless network, in which the device generates frequency hopping sequence y(j)...
US-9,614,579 Techniques for generation of a frequency hopping sequence
A device operated in a network using a channel hopping communication protocol may select a channel for each transmission by first generating and storing a...
US-9,614,556 Method and circuitry for transmitting data
Data transfer devices and methods for transferring data between first and second circuits are disclosed. A data transfer device includes a first circuit having...
US-9,614,517 Adaptive slew rate control for switching power devices
An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output...
US-9,614,510 Input path matching in pipelined continuous-time analog-to-digital converters
System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma...
US-9,614,506 Digital pre-compensation for voltage slewing in a power converter
Control logic for producing a digital input to a digital-to-analog converter (DAC) in a power converter system. The control logic selects from among a plurality...
US-9,614,368 Area-efficient active-FET ESD protection circuit
An electrostatic discharge (ESD) protection circuit includes a high power supply rail (VDD) and a low power supply rail (VSS). The ESD protection circuit...
US-9,613,685 Burst mode read controllable SRAM
A static random access memory (SRAM) includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage...
US-9,612,962 Performing cache bank operations in offset sequences from first bank
In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes...
US-9,612,879 System constraints-aware scheduler for heterogeneous computing architecture
Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics...
US-9,612,834 Processor with variable instruction atomicity
A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple...
US-9,612,339 Detecting satellite signals by storing signal sets spanning code period
A GNSS receiver configured to detect a presence of at least one GNSS satellite signal in a received signal is provided. The GNSS receiver includes a buffer...
US-9,612,338 Method to improve satellite signal detection
A method of acquiring a satellite signal in a GNSS receiver includes multiplying a received signal with a hypothesized doppler frequency signal to generate a...
US-9,612,283 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-9,612,282 Addressable tap with address detect and control. and gating circuitry
The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a...
US-9,609,670 Address space partitioning and filtering for discretionary wireless connection response
A system and method for providing wireless communications between a medical controller hub and an implant node are disclosed. The hub transmits signals to...
US-9,609,337 Temporal motion data candidate derivation in video coding
A method for derivation of a temporal motion data (TMD) candidate for a prediction unit (PU) in video encoding or video decoding is provided. The derived TMD...
US-9,609,333 Parsing friendly and error resilient merge flag coding in video coding
Methods and apparatus for parsing friendly and error resilient merge flag coding in video coding are provided. In some methods, in contrast to merging candidate...
US-9,609,306 Hierarchical binary structured light patterns
A method of image processing in a structured light imaging device is provided that includes receiving a captured image of a scene, wherein the captured image is...
US-9,608,525 Selected-parameter adaptive switching for power converters
A selected-parameter adaptively switched power conversion system, for example, includes a counter for determining a period of an output oscillation a power...
US-9,608,429 Logging ESD events
An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD...
US-9,608,158 Proximity sensor having light-blocking structure in leadframe and method of making same
A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is...
US-9,608,109 N-channel demos device
An n-channel DEMOS device a pwell finger defining a length and a width direction formed within a doped surface layer. A first nwell is on one side of the pwell...
US-9,608,105 Semiconductor structure with a doped region between two deep trench isolation structures
The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation...
US-9,608,088 Hybrid active-field gap extended drain MOS transistor
An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended...
US-9,607,926 Probe pad design to reduce saw defects
An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a...
US-9,607,847 Enhanced lateral cavity etch
A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is...
US-9,607,717 Reliability screening of ferroelectric memories in integrated circuits
A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined...
US-9,606,948 CAN bus edge timing control for dominant-to-recessive transitions
Structures and methods herein insert one or more parallel "recessive nulling" driver impedances across a controller area network (CAN) bus starting at the time...
US-9,606,803 Highly integrated scalable, flexible DSP megamodule architecture
This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include:...
US-9,606,796 Computer and methods for solving math functions
Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The...
US-9,606,563 Bandgap reference voltage failure detection
An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is...
US-9,606,193 Integrated dual axis fluxgate sensor using double deposition of magnetic material
A method of fabricating fluxgate devices to measure the magnetic field in two orthogonal, in plane directions, by using a composite-anisotropic magnetic core...
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