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Patent # Description
US-1,026,4275 Inter-prediction candidate index coding independent of inter-prediction candidate list construction in video coding
Methods are provided for inter-prediction candidate index coding independent of the construction of the corresponding inter-prediction candidate list, i.e., a...
US-1,026,4257 Video encoding
A system can include a given video processing engine to determine an estimated Quantization Parameter (QP) for a given row of Coding Tree Units (CTUs) in a...
US-1,026,3638 Lossless compression method for graph traversal
To enable lossless compression, an auxiliary bitmap is used to provide side information about the graph bitmap. Each bit in the auxiliary bitmap represents a...
US-1,026,3615 Circuit and method for driving a device through drive cycles
Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the...
US-1,026,3575 Programmable filter in an amplifier
The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output...
US-1,026,3555 Input vector set for position detection of PM motors
A method of determining angular position (0) of a rotor of an N-phase permanent magnet motor (PMM). A processor having an associated stored angular position...
US-1,026,3085 Transistor with source field plates and non-overlapping gate runner layers
A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or...
US-1,026,2957 Millimeter wave integrated circuit with ball grid array package including transmit and receive channels
An integrated circuit (IC) package includes an IC die and a wave channel that electrically couples the IC die to a solder ball array. The wave channel is...
US-1,026,2722 Fail-safe input/output (IO) circuit
The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a...
US-1,026,1126 3D tap and scan port architectures
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-1,025,7326 WLAN device with preamble decode-based receive suspend during undesired packets
A WLAN device includes a processor implementing a MAC layer and a PHY layer which is coupled to a transceiver including a receive (Rx) chain and a transmit (Tx)...
US-1,025,6821 Dual function analog or digital input/output buffer
A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without...
US-1,025,6815 Finger sensing device and method
A finger sensing device includes a first conductive plate, wherein the area between the finger and the first conductive plate increases in response to the...
US-1,025,6779 Multi-level class D amplifier
An amplifier includes a first transistor coupled to a first voltage source node and a second transistor coupled to a second voltage source node. The first and...
US-1,025,6723 Integrated circuit feed forward circuit with translinear cell
A power factor correction (PFC) integrated circuit having a feed forward circuit. The feed forward circuit comprises a first current source, a second current...
US-1,025,6717 Zero current detection circuit for converter soft switching control
A circuit includes a zero current detector (ZCD) circuit that senses an inductor current of an inductor and generates signal pulses indicating when an...
US-1,025,6337 Power transistor with terminal trenches in terminal resurf regions
A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type...
US-1,025,6188 Interconnect via with grown graphitic material
An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels....
US-1,025,6027 Embedded coil assembly and production method
An embodiment of coil assembly includes a laterally disposed ferrite ring having a central opening. A laterally disposed annular conductive member is positioned...
US-1,025,5888 Merging multiple exposures to generate a high dynamic range image
A method of generating a high dynamic range (HDR) image is provided that includes capturing a long exposure image and a short exposure image of a scene,...
US-1,025,5511 Real time traffic sign recognition
Advanced driver assistance systems need to be able to recognize and to classify traffic signs under real time constraints, and under a wide variety of visual...
US-1,025,5078 Operating a pipeline flattener in order to track instructions for complex breakpoints
A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a...
US-1,025,4341 Scan input stimulus registers, test control register controlling compressor circuitry
Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The...
US-1,025,1280 Integrated circuit with micro inductor and micro transformer with magnetic core
An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor...
US-1,025,1258 Dielectric waveguide core between ground planes secured in a channel
An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and...
US-1,025,1226 Method and apparatus for calculating an average value of an inaccessible current from an accessible current
In a power converter, a circuit determines an average value of an inaccessible current from an average value of an accessible current and a value of the...
US-1,025,0978 Voice coil temperature control based on an estimated voice coil temperature and a threshold
A system includes a gain control circuit configured to dynamically select a gain value based on an estimated temperature for a speaker voice coil, a base gain...
US-1,025,0276 Segmented digital-to-analog converter
Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation...
US-1,025,0273 Band specific interleaving mismatch compensation in RF ADCs
An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a...
US-1,025,0253 Method and apparatus for a brown out detector
The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to...
US-1,025,0211 Beta equalization to reduce non-linear distortions of bipolar transistor amplifiers
Reducing non-linear distortions of an electronic device by performing at least the following: receiving, at an output stage circuit of an amplifier, an input...
US-1,025,0192 Class-E outphasing power amplifier with efficiency and output power enhancement circuits and method
An outphasing amplifier includes a first class-E power amplifier having an output coupled to a first conductor and an input receiving a first RF drive signal. A...
US-1,024,9621 Dummy contacts to mitigate plasma charging damage to gate dielectrics
A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD) layer...
US-1,024,9610 IGBT coupled to a reverse bias device in series
In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal,...
US-1,024,9607 Internally stacked NPN with segmented collector
An integrated circuit includes a stacked NPN having an upper NPN connected to a lower NPN. The upper NPN includes an upper collector, an upper base, and an...
US-1,024,9504 Etching and mechanical grinding film-layers stacked on a semiconductor substrate
In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the...
US-1,024,8876 Method and apparatus for avoiding non-aligned loads using multiple copies of input data
A method of determining a summation of pixel characteristics for a rectangular region of a digital image includes determining if a base address for a data...
US-1,024,8872 Estimation of time to collision in a computer vision system
A method for estimating time to collision (TTC) of a detected object in a computer vision system is provided that includes determining a three dimensional (3D)...
US-1,024,8583 Simultaneous video and bus protocols over single cable
Method and systems are disclosed for transporting simultaneous video and bus protocols over a single cable. At least some of the illustrative embodiments are...
US-1,024,7779 Tap, decoder providing SC and SE to scan path circuits
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access...
US-1,024,4591 Voltage/current regulator supplying controlled current with PVT adjusted headroom
A voltage/current regulator supplying controlled current with PVT headroom adjustment. In an example application, an LED backlight driver controls ILED string...
US-1,024,4246 Sub-pictures for pixel rate balancing on multi-core platforms
A method for decoding a compressed video bit stream in a video decoder to recover a video sequence, the video decoder including a plurality of decoder...
US-1,024,3573 Phase syncronizing PLL output across reference and VCO clock domains
Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input...
US-1,024,3469 Adaptive burst generation for use with a DC-output converter
These teachings apply with respect to a direct current (DC)-output converter and provide for adjusting a number of switching pulses per burst cycle as a...
US-1,024,3464 Power regulator with prevention of inductor current reversal
A controller including a voltage synthesizer for a switching regulator includes a synthesizer input to be coupled to an input of the regulator. First and second...
US-1,024,3463 Non-inverting buck-boost converter control
An apparatus comprises a voltage supply configured to provide an input voltage, a buck-boost converter coupled to the voltage supply and comprising an inductor,...
US-1,024,3048 High dose antimony implant through screen layer for n-type buried layer integration
A microelectronic device having an n-type buried layer (NBL) is formed by forming a thin screen layer on the top surface of the substrate. Antimony is implanted...
US-1,024,2147 Multilevel via placement with improved yield in dual damascene interconnection
A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer...
US-1,024,1791 Low energy accelerator processor architecture
An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having...
US-1,024,0991 Vibration and dynamic acceleration sensing using capacitors
The present disclosure relates to an apparatus comprising at least one sensing capacitor and a controller, wherein the controller is configured to receive a...
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