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Patent # Description
US-9,755,516 Switched mode DCDC converter efficiency improvement by adaptive driver stage
In a switched mode inductive DCDC converter having a first mode that conducts a first current path through an inductor and through a first switch, and a second...
US-9,753,120 Method to "zoom into" specific objects of interest in a radar
The disclosure provides a radar apparatus fur estimating a distance of the one or more obstacles in a range of interest. The radar apparatus includes a local...
US-9,749,019 Methods and apparatus for determining nearfield localization using phase and RSSI delivery
Methods and apparatus to determine nearfield localization using phase and received signal strength indication (RSSI) diversity are disclosed. An example method...
US-9,748,966 Histogram based error estimation and correction
A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an...
US-9,748,965 Pipeline ADC and reference load balancing circuit and method to balance reference circuit load
Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects...
US-9,748,950 Gate energy recovery
Embodiment of the inventive subject matter include an apparatus comprising a first switch, a second switch, a third switch, and a transistor. The first switch...
US-9,748,842 Sense circuit for voltage converter
A system including a first power transistor including a gate, a second power transistor including a gate and connected in series with the first power...
US-9,748,841 Multilevel boost DC to DC converter circuit
Described examples include DC to DC converters and systems with switching circuitry formed by four series-connected switches, inductors connected between the...
US-9,748,686 BGA spring probe pin design
An improved BGA spring probe pin with a spring actuated solder ball receptacle that grips the sides of the solder ball during probing. A method of operating a...
US-9,748,376 Power FET with integrated sensors and method of manufacturing
A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors...
US-9,748,181 Methods and apparatus for crack propagation prevention and enhanced particle removal in scribe line seals
An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated...
US-9,747,736 Multiple-band identification and ranging
A long-range power-efficient multiple-band identification system and method includes, for example, a base-station control module and paired electronic key fob....
US-9,747,515 Efficient feature point selection
Systems and methods are provided for selecting feature points within an image. A plurality of candidate feature points are identified in the image. A plurality...
US-9,747,507 Ground plane detection
A ground plane detection system including an imaging device operable to generate at least two images of a scene and an image processing assembly operable to...
US-9,747,255 Inverse transformation using pruning for video coding
A method for decoding an encoded video bit stream in a video decoder is provided that includes determining a scan pattern type for a transform block to be...
US-9,747,220 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices
A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a...
US-9,746,868 Single inductor multiple output discontinuous mode DC-DC converter and process
A system comprising an ambient energy source, a power supply, and a power storage device. The ambient energy source is coupled to a first terminal end of an...
US-9,746,862 Voltage-to-current converter
A voltage-to-current converter includes an input stage having a first input and a second input. The first input is connectable to a reference voltage, wherein...
US-9,746,518 Scan path interface circuit with strobe sequencer and two registers
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and...
US-9,746,517 IC interposer with TAP controller and output boundary scan cell
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement...
US-9,746,515 Address-command port connected to trace circuits and tap domains
An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI...
US-9,743,530 Chip capacitors
A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of...
US-9,742,785 Power line communication (PLC) network nodes using cipher then segment security
Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates...
US-9,741,791 Latchup reduction by grown orthogonal substrates
An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first...
US-9,741,790 Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect
Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions...
US-9,741,787 Methods and apparatus for high voltage integrated circuit capacitors
High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate...
US-9,741,724 SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array
An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as...
US-9,741,718 High voltage CMOS with triple gate oxide
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a...
US-9,741,643 Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns
A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad...
US-9,741,624 Spacer shaper formation with conformal dielectric film for void free PMD gap fill
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
US-9,741,557 Silicon nitride process for reduction of threshold shift
A semiconductor device has a substrate with a semiconductor material. The semiconductor device includes a field effect transistor in and on the semiconductor...
US-9,741,430 Static random access memory with reduced write power
A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller....
US-9,741,358 Method and system for interference suppression using blind source separation
A method of interference suppression is provided that includes receiving a first audio signal from a first audio capture device and a second audio signal from a...
US-9,740,887 Methods and systems to restrict usage of a DMA channel
In at least some embodiments, a system comprises a processor and a direct memory access (DMA) subsystem coupled to the processor. The system further comprises a...
US-9,740,261 USB power delivery dead-battery control
A method of power delivery. Port controllers each include a state machine, an IO pin, a receptacle supply pin receiving power from a receptacle, and a gate...
US-9,740,236 Dual window watchdog timer
Systems and methods for a Dual Window Watchdog Timer (DWWDT) are described. In some embodiments, a method may include running a first counter in a first clock...
US-9,739,832 Test messaging demodulate and modulate on separate power pads
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device....
US-9,738,339 Side stand indicator for a two-wheel vehicle
A two-wheel vehicle includes a frame and a metallic side stand, rotatable within a bracket attached to the frame. The metallic side stand is rotatable between a...
US-9,736,898 Circuit and method for driving a light-emitting diode
Circuits and methods for driving an LED from a secondary side of a transformer are disclosed herein. An embodiment of the method includes monitoring an input...
US-9,735,844 Channel feedback for coordinated multi-point transmissions
A method of Coordinated Multipoint (CoMP) communication between a base station having a plurality of points with at least one user equipment (UE). At least one...
US-9,735,802 Overload detection and correction in delta-sigma analog-to-digital conversion
A voltage-controlled oscillator-based delta-sigma analog-to-digital converter (VCO-based .DELTA..SIGMA. ADC) includes a VCO-based quantizer that includes delay...
US-9,735,794 Analog-to-digital converter with an increased resolution first stage
One example includes a pipelined analog-to-digital converter device. The pipelined analog-to-digital converter device includes a capacitive digital-to-analog...
US-9,735,753 Baluns for RF signal conversion and impedance matching
A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary...
US-9,735,600 Method for limiting battery discharging current in battery charger and discharger circuit
A power supply system includes a rechargeable battery to deliver a supply current to a load and a circuit to limit a discharge current when the rechargeable...
US-9,735,265 Reduced area power devices using deep trench isolation
An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with...
US-9,735,172 Method to match SOI transistors using a local heater element
An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for...
US-9,735,159 Optimized layout for relaxed and strained liner in single stress liner technology
An integrated circuit and method with a single stress liner film and a stress relief implant where the distance of the stress relief implant to the transistors...
US-9,734,896 Circuits and methods for performance optimization of SRAM memory
In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal to...
US-9,734,429 Method, system and computer program product for detecting an obstacle with a camera
For detecting an obstacle with a camera, a first image is viewed by the camera at a first location during a first time. Points on a surface would project onto...
US-9,734,265 Method and apparatus having enhanced oscillator phase noise using high Vt MOS devices
A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output...
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