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Patent # Description
US-9,465,742 Synchronizing barrier support with zero performance impact
The barrier-aware bridge tracks all outstanding transactions from the attached master. When a barrier transaction is sent from the master, it is tracked by the...
US-9,465,741 Multi processor multi domain conversion bridge with out of order return buffering
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each...
US-9,462,956 Calculating heart rate from acceleration signals containing cardiac activity signals
A heart monitor includes a single chest accelerometer (210), an analog signal conditioning and sampling section (215) responsive to said accelerometer to...
US-9,461,861 Time-domain windowing function
A smart utility network (SUN) device that includes an orthogonal frequency-division multiplexing (OFDM)-based transmitter. The OFDM-based transmitter including...
US-9,461,628 Single ended charge to voltage front-end circuit
Charge to voltage conversion integrator circuitry for data acquisition front-end and other applications to provide a single-ended up a voltage using an input...
US-9,461,439 Optoelectronic packages having magnetic field cancelation
A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to...
US-9,461,131 High quality deep trench oxide
An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio...
US-9,461,060 Feed-forward bidirectional implanted split-gate flash memory cell
A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second...
US-9,461,046 LDMOS device with graded body doping
A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is...
US-9,461,035 High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit
A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding...
US-9,461,032 Bipolar ESD protection device with integrated negative strike diode
A bipolar ESD protection device includes a substrate having a p-type epi layer thereon including an epi region over an n-buried layer (NBL). An n-type isolation...
US-9,460,962 Substrate contact etch process
A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step...
US-9,460,720 Powering-up AFE and microcontroller after comparing analog and truncated sounds
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. The received analog signal is evaluated using...
US-9,459,886 Autonomous sleep mode
A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely...
US-9,459,352 Multi-sensor proximity sensing using a near zone light sensor and a far zone light sensor
An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light...
US-9,459,339 Kalman filter for indoor positioning
A position estimation method for indoor positioning includes filtering an initial position estimate that includes a corresponding covariance that reflects the...
US-9,456,432 Clock synchronization and centralized guard time provisioning
Embodiments of the invention provide a method to accommodate clock drift and guard time in a centralized fashion. In one embodiment, a device is adapted to...
US-9,456,257 Device for transferring power from a first circuit to a second circuit
A power transfer system for transferring power from a first circuit to a second circuit by a differential signal generated in the first circuit includes a first...
US-9,455,851 Efficient encoding/decoding algorithm for MTS constrained MFSK communications
A method of encoding a data signal is disclosed. The method includes selecting a set of M ultrasonic frequencies, wherein each of the M ultrasonic frequencies...
US-9,455,721 FLL oscillator/clock with an FLL control loop including a switched capacitor resistive divider
An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an...
US-9,455,720 Universal oscillator
The disclosure provides a universal oscillator. The oscillator includes an amplifier array. The amplifier array includes one or more amplifiers. A control logic...
US-9,455,332 LDMOS transistor and method of forming the LDMOS transistor with improved Rds*Cgd
The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a...
US-9,455,312 Multiple depth vias in an integrated circuit
An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with...
US-9,455,252 Combining ZTCR resistor with laser anneal for high performance PMOS transistor
An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with...
US-9,455,222 IC having failsafe fuse on field dielectric
A fuse circuit includes a substrate, a top semiconductor layer doped a first conductivity type having a well doped a second conductivity type formed therein...
US-9,455,021 Array power supply-based screening of static random access memory cells for bias temperature instability
A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory...
US-9,454,437 Non-volatile logic based processing device
A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a...
US-9,454,203 Method, system and computer program product for reducing consumption of battery power
An information handling system is powered by a battery. In response to determining that a remaining amount of power within the battery has fallen below a first...
US-9,454,135 Manufactureable long cell with enhanced sensitivity and good mechanical strength
A method of providing a manufactureable long vapor cell with enhanced sensitivity and good mechanical strength, wherein the method provides a structure that...
US-9,454,003 Lense module
A lens assembly includes a first lens and a transducer attached to the first lens. A method of cleaning a lens includes vibrating the lens with a transducer...
US-9,453,882 Scan paths with gating, enable, and select decode control circuits
An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the...
US-9,453,867 Processor chip with ultrasound transducer for ultrasound chip debugging
A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to...
US-9,451,283 Method, system and computer program product for selecting a motion vector in scalable video coding
From among blocks within a region of a first image, a search is performed for a highest scoring match to a block of a second image. Searching for the highest...
US-9,451,181 Optimized algorithm for construction of composite video from a set of discrete video sources
A method includes reading a composite video descriptor data structure and a plurality of window descriptor data structures. The composite video descriptor data...
US-9,450,708 System and method for avoiding hidden node collisions in a communication network
Method and apparatus for avoiding hidden node collisions in a communication network. A network communication device includes a packet transmitter. The packet...
US-9,450,651 Inductive structures with improved common mode transient immunity
In a first inductive structure, a first data coil includes: a first portion for conducting a first common mode current in a first direction; and a second...
US-9,450,546 System, method and device for power amplification of a signal in an integrated circuit
According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of...
US-9,450,487 DC to DC converter
A DC to DC converter includes an inductor having a first terminal and a second terminal, the first terminal coupled to an input of the DC to DC converter and...
US-9,450,082 Integrated termination for multiple trench field plate
A semiconductor device includes a vertical MOS transistor with a plurality of parallel RESURF drain trenches separated by a constant spacing in a vertical drain...
US-9,449,137 Buffered conduits for high throughput channel implementation, crosstalk de-sensitization and late timing fixes...
A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and...
US-9,448,767 Three-term predictive adder and/or subtracter
A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2.sup.k, where k is a...
US-9,448,484 Sloped electrode element for a torsional spatial light modulator
A method of forming a micro-electromechanical systems (MEMS) pixel, such as a DMD-type pixel, by depositing a photoresist spacer layer upon a substrate. The...
US-9,448,284 Method and apparatus for test time reduction using fractional data packing
An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo...
US-9,446,947 Use of metal native oxide to control stress gradient and bending moment of a released MEMS structure
A MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first...
US-9,445,405 Uplink synchronization management in wireless networks
In at least some embodiments, a wireless networking system is provided. The wireless networking system includes a base-station and a plurality of user devices...
US-9,444,669 Peak to average power ratio reduction of OFDM signals
A method includes processing an input sequence of samples of an orthogonal frequency division multiplexing signal (OFDM) to reduce a peak to average power ratio...
US-9,444,650 Methods and apparatus to allocate reference signals in wireless communication systems
Methods and apparatus to allocate reference signals in wireless communication systems are disclosed. A disclosed example method comprises applying a first...
US-9,444,494 Systems and methods for network coding using convolutional codes
A network coding method includes receiving a plurality of input packets each having a packet length. Encoding the plurality of input packets by applying a...
US-9,444,481 Analog to digital converter
An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a...
US-9,444,478 Voltage regulator with load compensation
A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage...
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