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Programmable ESD protection circuit
An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a...
Low-cost CMOS structure with dual gate dielectrics and method of forming
the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
Deep trench with self-aligned sinker
A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench...
Fabrication flow based on metal gate process for making low cost flash
An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions...
High tilt angle plus twist drain extension implant for CHC lifetime
An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one...
System and method for managing cache
A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter...
Processor power measurement
A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The...
Apparatus and method for optimizing use of NVDC chargers
A method includes detecting removal or depletion of a power supply associated with a powered device. The powered device is configured to receive power from a...
Short-circuit protection for voltage regulators
Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error...
Power-gated electronic device
A power-gated electronic device and a method of operating the same is provided. The power-gated electronic device comprises a low drop out voltage power supply...
Atomic clocks and magnetometers with vapor cells having condensation sites
in fluid communication with a cavity...
A vapor cell for installation in an atomic clock or a magnetometer. The vapor cell includes a top plate, a center plate, and a bottom plate defining a cavity...
Programmable wavelet tree
An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to...
Determining gas absorption line from separate and alternating RF signals
A method to detect a gas absorption line that includes alternately transmitting and sweeping two radio frequency (RF) signals through an absorption cell,...
Video output supervisor
A video output supervisor includes a test region indicator for verifying that the commanded output to specific areas of a display is valid. Areas reserved...
Power line communication (PLC) network nodes using cipher then segment
Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates...
4TX codebook enhancement in LTE
Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based...
Method and apparatus for compensating offset drift with temperature
The disclosure provides an analog to digital converter (ADC). The ADC includes a comparator that receives a threshold voltage. A set of elementary capacitors is...
A frequency detection technique includes generating first and second signals such that a frequency of the first signal is the same as a frequency of the second...
Reconfigurable power switch chains for efficient dynamic power saving
Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for...
Low area flip-flop with a shared inverter
A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock...
Tunable quadrature oscillator
A tunable quadrature oscillator includes a first oscillator having an output, a second oscillator having an output, and a variable gain amplifier. The variable...
Active ESD protection circuit with blocking diode
An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a...
Stacked synchronous buck converter having chip embedded in outside recess
A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor...
Flexible arbitration scheme for multi endpoint atomic accesses in
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
DC to DC converter with pseudo constant switching frequency
A method for a DC to DC converter with a pseudo constant switching frequency is disclosed herein. For example, some embodiments provide a DC to DC converter...
Taps with class T0-T2 and T3, T4(W), and T5(W) capabilities
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
Transporting ordered test data, mode select, ready, precharge packet bits
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to...
Structure for implementing openflow all group buckets using egress flow
An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets....
System and method for preamble detection in MIMO narrowband power line
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
Data transfer clock recovery for legacy systems
The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate...
NLOS wireless backhaul uplink communication
A method for uplink (UL) wireless backhaul communication at a wireless backhaul remote unit in a radio access network comprising receiving a configuration for...
Phase shifted coarse/fine clock dithering responsive to controller select
A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an...
Low power scheme to protect the low voltage capacitors in high voltage IO
An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being...
Clock data recovery system
A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal;...
Controllable wide frequency range oscillator
A circuit includes a ring oscillator that includes a plurality of delay stages coupled in series to generate an output frequency for the ring oscillator. A...
Shared bootstrap capacitor for multiple phase buck converter circuit and
A multiple phase dc to dc converter with a shared bootstrap capacitor. In an embodiment, a multiple phase buck converter is disclosed including a plurality of n...
Short-circuit protection system for power converters
One example includes a power converter system. The system includes a switching circuit configured to activate at least one power supply switch in response to a...
Wafer substrate removal
A semiconductor device is formed on a semiconductor substrate, including a primary portion of the substrate. An active component of the semiconductor device is...
Alternating tap-cell strategy in a standard cell logic block for area
An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a...
Method for designing diodes
A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating...
Power switch with source-bias mode for on-chip powerdomain supply drooping
This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit...
Magnetic field sensor linearization architecture and method
A method of processing an output signal and a readout circuit for a magnetic field sensor are disclosed. The purpose of the readout circuit is to generate a...
IC die with tap lock, test, scan, and up circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
Semiconductor test system and method
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
Infrared sensor structure and method
A radiation sensor (27) includes a radiation sensor chip (1) including first (7) and second (8) thermopile junctions connected to form a thermopile (7,8). The...
Graphics initialization for wireless display devices
A method of optimizing bandwidth of a wireless link between a display device and an image data player. The display device is configured with one or more...
Hybrid automatic repeat request acknowledge resource allocation for
enhanced physical downlink control channel
A method and apparatus of wireless communication between a base station and at least one user equipment. The method includes: transmitting an enhanced physical...
SNR calculation in impulsive noise and erasure channels
A device coupled to a noisy channel having periodic impulse noise in a network may estimate an effective signal to noise ratio (SNR) by receiving a packet of...
Delta sigma modulator apparatus and method to mitigate DAC error induced
offset and even order harmonic distortion
Delta sigma modulators, apparatus and methods mitigate DAC error induced offset and even order harmonic distortion in a delta sigma modulator by chopping a...
Method for calibrating a pipelined continuous-time sigma delta modulator
Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating...