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Patent # Description
US-7,498,648 Mirror-based projection system with a programmable control unit for controlling a spatial light modulator
A projection system is disclosed herein. The projection system employs a spatial light modulator comprising an array of individually addressable pixels for...
US-7,498,639 Integrated BiCMOS semiconductor circuit
An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor...
US-7,498,264 Method to obtain fully silicided poly gate
The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material 160 over gate...
US-7,498,219 Methods for reducing capacitor dielectric absorption and voltage coefficient
Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through...
US-7,498,203 Thermally enhanced BGA package with ground ring
The invention provides thermally enhanced BGAs and methods for their fabrication with a ground ring suitable for operably coupling to either the frontside or...
US-7,496,930 Accessing device driver memory in programming language representation
In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application...
US-7,496,822 Apparatus and method for responding to data retention loss in a non-volatile memory unit using error checking...
In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking...
US-7,496,360 Multi-function telephone
A wireless mobile telephone for connecting to multiple networks that includes a cellular module for routing calls through a cellular telephone network, a...
US-7,496,154 Power and area efficient receiver circuit having constant hysteresis for noise rejection
A hysteresis receiver containing two inverters and a logic controller. The inverters are implemented with threshold voltages equaling Vil and Vih, which together...
US-7,496,134 Computationally and memory efficient tone ordering scheme
An integrated circuit 18 is provided that includes a memory 32 and a memory modification component 33. The memory 32 maintains a bits count, a gain, and a tone...
US-7,495,749 Rapid method for sub-critical fatigue crack growth evaluation
In a method and system for evaluating sub-critical fatigue crack growth in a semiconductor device, a plurality of energy pulses generated by an energy source are...
US-7,495,589 Circuit and method for gain error correction in ADC
Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on...
US-7,495,508 Switched capacitor notch filter circuits
Switched capacitor notch filter circuits are disclosed. An example switched capacitor notch filter circuit described herein includes a switched capacitor...
US-7,495,458 Probe card and temperature stabilizer for testing semiconductor devices
One aspect of the invention provides an apparatus that includes a probe card having probe needles associated therewith. A temperature stabilizer element is...
US-7,495,429 Apparatus and method for test, characterization, and calibration of microprocessor-based and digital signal...
A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and...
US-7,494,905 Method for preparing a source material including forming a paste for ion implantation
The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method...
US-7,494,882 Manufacturing a semiconductive device using a controlled atomic layer removal process
A method for manufacturing a semiconductive device comprising forming a mask for a semiconductive device structure over a layer of a semiconductor substrate and...
US-7,494,829 Identification of outlier semiconductor devices using data-driven statistical characterization
Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein. At least some...
US-7,493,575 Method for generating and evaluating a table model for circuit simulation
A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table...
US-7,493,539 Separately controlled scan paths of functional registers providing stimulus/response data
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-7,493,538 Low power scan process with connected stimulus and scan paths
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,493,537 Propagation test strobe circuitry with boundary scan circuitry
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-7,493,536 IC input memory with dual data and dual control inputs
An electronic integrated circuit includes a signal path connected between the functional logic and an external input terminal, which signal path includes a...
US-7,493,535 JTAG circuit transferring data between devices on TCK terminals
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-7,493,476 Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence
A processor is provided that includes decode logic coupled to an instruction cache and a micro-sequence vector table including entries for each bytecode in an...
US-7,492,915 Dynamic sound source and listener position based audio rendering
This invention describes the use of dynamic sound source and listener position (DSSLP) based audio rendering to achieve high quality audio effects using only a...
US-7,492,848 Method and apparatus for efficient multi-stage FIR filters
An interpolation filter without a FIFO memory is configured as a cascade arrangement of simpler interpolation sub-filters that are operated in reverse order. The...
US-7,492,843 Method of synchronization for packet based, OFDM wireless systems with multiple receive chains
A system for synchronizing a wireless receiver is provided. The system includes a first antenna (101a) and a second antenna (101b) to receive wireless signals...
US-7,492,799 Light-emitting element driver
The bias current of a current injection-type light-emitting element is set very close to the threshold current, and to guarantee a stable optical output and...
US-7,492,736 System and method for access and management of beacon periods in distributed wireless networks
The present application describes a system and method of managing beacon periods in a distributed wireless network. According to an embodiment, devices move...
US-7,492,703 Noise analysis in a communication system
A system is provided to automatically estimate performance of a receiver for receiving input signals, the input signals having a carrier frequency and a baud...
US-7,492,702 Versatile system for optimizing data fragmentation in digital communications
The present invention provides a versatile system for optimizing data fragmentation in a digital communications--particularly OFDM communications--system. A...
US-7,492,217 On-the-fly introduction of inter-channel delay in a pulse-width-modulation amplifier
A multiple-channel audio processor (10) and an associated plurality of power stages (22) in an audio system are disclosed. The audio processor (10) includes a...
US-7,492,108 System and method for driving light-emitting diodes (LEDs)
System and method for improving efficiency in driving LEDs. A preferred embodiment comprises a switch current regulator coupled to a current control signal...
US-7,491,970 IC with comparator receiving expected and mask data from pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the...
US-7,491,635 Method for forming a fully silicided gate and devices obtained thereof
A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the...
US-7,489,720 Method for transmit pulse design for ultra-wideband communications
Method for designing transmission pulses for ultra-wideband communications systems. A preferred embodiment comprises specifying a spectral description for the...
US-7,489,584 High performance, low-leakage static random access memory (SRAM)
Systems and methods are provided for reducing leakage current and maintaining high performance in a static random access memory (SRAM). One embodiment discloses...
US-7,489,180 Systems and methods for efuse fusing time reduction
Various systems and methods for device configuration are disclosed herein. For example, some embodiments of the present invention provide semiconductor devices...
US-7,489,009 Multiple-gate MOSFET device with lithography independent silicon body thickness
Multi-gate MOS transistors and fabrication methods are described, in which the transistor semiconductor body thickness or width is lithography independent,...
US-7,488,636 Broken die detect sensor
A broken trim die tool detection sensor. The lands of the tie bar die connect with the leads of the unit to form switches. The states of these switches indicate...
US-7,488,623 Integrated circuit chip packaging assembly
An integrated circuit chip packaging assembly having a first and second package side. An integrated circuit chip has a substrate side and an active circuit side....
US-7,487,421 Emulation cache access for tag view reads
A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters...
US-7,487,417 Digital storage element with enable signal gating
A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data...
US-7,485,963 Use of supercritical fluid for low effective dielectric constant metallization
An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step...
US-7,484,053 Cross-referencing cache line addresses with corresponding names
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache...
US-7,483,819 Representing data having multi-dimensional input vectors and corresponding output element by piece-wise polynomials
Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an...
US-7,483,587 Iterative filtering for dithered imaging
Filtering image information to generate a dithered image includes receiving input image information corresponding to an image generated using a first array...
US-7,483,508 All-digital frequency synthesis with non-linear differential term for handling frequency perturbations
An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word...
US-7,483,332 SRAM cell using separate read and write circuitry
The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry...
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