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Patent # Description
US-7,512,268 System and method for local value adjustment
In accordance with the teachings of the present invention, a system and method for local value adjustment are provided. In one embodiment, the method includes...
US-7,512,148 Weighted round-robin arbitrator
A weighted round-robin arbitrator for a plurality of data queue includes an arbitration table comprising a plurality of entries. Each entry represents a time...
US-7,512,078 Flexible ethernet bridge
A bridge operates in either VLAN aware mode or VLAN unaware mode as specified by a user. A packet is received in a priority tagged format containing an...
US-7,512,030 Memory with low power mode for WRITE
The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to...
US-7,511,769 Interframe noise reduction for video
A system to reduce noise includes a noise measurement device that provides a measure of noise associated with a digital input video signal. A noise reduction...
US-7,511,648 Integrating/SAR ADC and method with low integrator swing and low complexity
A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating...
US-7,511,647 Dynamic element matching method and device
The invention provides an improved dynamic element matching (DEM) device. The DEM device performs dynamic element matching processing at a second timing rate...
US-7,511,552 Method and apparatus of a level shifter circuit having a structure to reduce fall and rise path delay
A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level...
US-7,511,527 Methods and apparatus to test power transistors
Methods and apparatus to test power transistors of integrated circuits on a wafer are disclosed. An example method comprises measuring a drain-source on...
US-7,511,350 Nickel alloy silicide including indium and a method of manufacture therefor
The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The...
US-7,510,923 Slim spacer implementation to improve drive current
Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain...
US-7,509,565 Wireless access modem having downstream channel resynchronization method
A resynchronization method for use in a data communication system having a first device configured to transmit data at a symbol rate to a second device. The...
US-7,509,549 Dynamic frequency scaling for JTAG communication
A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the...
US-7,509,391 Unified memory management system for multi processor heterogeneous architecture
A multi-processor system 8 includes multiple processing devices, including DSPs (10), processor units (MPUs) (21), co-processors (30) and DMA channels (31). Some...
US-7,509,101 Method and apparatus for reducing leakage in a direct conversion transmitter
Methods and apparatus for reducing the amount of leakage in a transmitter are disclosed. In one embodiment, a wireless transmitter is comprises: a divider...
US-7,508,877 Methods and apparatus for self-inverting turbo code interleaving with high separation and dispersion
The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods...
US-7,508,781 Power saving mechanism for wireless LANs via schedule information vector
A new protocol system and method is described that utilizes a Schedule Information Vector (SIV) protocol for saving power in wireless local area networks. The...
US-7,508,728 Methods and apparatus to provide refresh for global out of range read requests
Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell...
US-7,508,698 Memory array with a delayed wordline boost
Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets...
US-7,508,330 Apparatus and method for improving performance of sigma-delta modulators having non-ideal components
In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements...
US-7,508,063 Low cost hermetically sealed package
Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package...
US-7,508,027 Single-poly EPROM device and method of manufacturing
The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned...
US-7,508,013 Versatile system for cross-lateral junction field effect transistor
The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage,...
US-7,507,605 Low cost lead-free preplated leadframe having improved adhesion and solderability
A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack...
US-7,506,238 Simplified LDPC encoding for digital communications
Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix...
US-7,506,131 Reformat logic to translate between a virtual address and a compressed physical address
In some embodiments, reformat logic comprises a plurality of registers and translation logic that accesses the registers. The translation logic receives a memory...
US-7,505,526 Methods and apparatus for self-inverting turbo code interleaving with high separation and dispersion
The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods...
US-7,505,525 Methods and apparatus for self-inverting turbo code interleaving with high separation and dispersion
The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods...
US-7,504,977 Hybrid delta-sigma/SAR analog to digital converter and methods for using such
Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first...
US-7,504,895 Multi-phase interleaved oscillator
An oscillator for synchronizing and controlling a multi-phase, interleaved power supply system that has a plurality of power sources. The oscillator includes a...
US-7,504,857 Functional cells for automated I/O timing characterization of an integrated circuit
Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive...
US-7,504,716 Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
A semiconductor device comprising a semiconductor chip (101) assembled on a first copper cuboid (110); the cuboid has sides of a height (111). The device further...
US-7,504,713 Plastic semiconductor packages having improved metal land-locking features
A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent...
US-7,504,339 Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits
A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a...
US-7,504,329 Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET
Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and...
US-7,504,283 Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus...
US-7,502,727 Tracing user change of program counter during stop event
This invention tracks emulation changes in the program counter of the central processing unit of a data processor during emulation halt. The sequence includes:...
US-7,502,591 Multi-mode radio piconet/scatternet
A communication system 100 allows for heterogeneous piconets/scattenets 100 where in multiple modes 110, 112 of transmission, one of Bluetooth 110 and one or...
US-7,502,337 Intelligent voice network monitoring using echo cancellation statistics
Monitoring voice quality passively using line echo cancellation data across a telecommunications network and reporting monitoring data to a central network...
US-7,502,247 Memory array with a delayed wordline boost
Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets...
US-7,502,155 Antireflective coating for semiconductor devices and method for the same
According to one embodiment of the present invention, a semiconductor device includes a first layer of dielectric material disposed upon an upper surface of a...
US-7,502,076 Method and apparatus for a digital display
A method and apparatus for a digital video display. A digital display device receives an analog signal representing an image formed of pixels in video lines and...
US-7,502,075 Video processing subsystem architecture
A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The...
US-7,501,981 Methods and apparatus to detect and correct integrity failures in satellite positioning system receivers
Methods and apparatus to detect integrity failures in satellite position system (SPS) receivers are disclosed. An example method comprises estimating a position...
US-7,501,970 Digital to analog converter architecture and method having low switch count and small output impedance
A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to...
US-7,501,965 Correcting for errors that cause generated digital codes to deviate from expected values in an ADC
Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored...
US-7,501,964 Entropy coding for digital codecs
A method and systems are provided for efficiently implementing content adaptive variable length coding on a modern processor. Some embodiments comprise encoding...
US-7,501,324 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-7,500,130 Cycle-accurate real-time clocks and methods to operate the same
Cycle-accurate real-time clocks and methods to operate the same are disclosed. An example real-time clock comprises a first counter to count cycles of a...
US-7,500,085 Identifying code for compilation
A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further...
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