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Patent # Description
US-7,571,419 Methods and systems for performing design checking using a template
A design application improves design checking by utilizing a template. During the checking process, the design application divides the design layout into...
US-7,571,366 Sequential signals selecting mode and stopping transfers of interface adaptor
A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states...
US-7,571,365 Wafer scale testing using a 2 signal JTAG interface
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously...
US-7,571,364 Selectable JTAG or trace access with data store and output
An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and...
US-7,571,094 Circuits, processes, devices and systems for codebook search reduction in speech coders
An electronic circuit includes storage circuitry and a speech coder coupled with the storage circuitry to have a codebook with sets of track location numbers for...
US-7,570,646 Apparatus and method for an interface unit for data transfer between a host processing unit and a multi-target...
A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous...
US-7,570,527 Static random-access memory having reduced bit line precharge voltage and method of operating the same
A bit line precharge circuit, a method of precharging a bit line and an SRAM device incorporating the circuit or the method. In one embodiment, the bit line...
US-7,570,410 High brightness display systems using multiple spatial light modulators
The display system separates reflected and transmitted light from a color wheel of the display system; and modulates the separated reflected and transmitted...
US-7,570,182 Adaptive spectral noise shaping to improve time to digital converter quantization resolution using dithering
A novel and useful apparatus for and method of improving the quantization resolution of a time to digital converter in a digital PLL using noise shaping. The TDC...
US-7,570,113 Overload recovery circuit for folded cascode amplifiers
In a method and apparatus for rapidly recovering an improved amplifier from an overload condition, a cascode amplifier (CASA) having a pair of inputs and an...
US-7,570,108 Apparatus for regulating voltage
An apparatus for regulating voltage for at least one differential transistor pair having a voltage follower buffer, the voltage follower section having a first...
US-7,570,100 Potential and rate adjust header switch circuitry reducing transient current
System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as...
US-7,570,076 Segmented programmable capacitor array for improved density and reduced leakage
A capacitor circuit and method to reduce layout area, leakage current, and to improve yield is disclosed. The circuit includes an output terminal (100), a...
US-7,570,043 Switches bidirectionally connecting external lead to PLL voltage tune line
An integrated circuit, a phase locked loop, a voltage tune probe and a method of screening an integrated circuit employing a phase locked loop thereof. In one...
US-7,569,918 Semiconductor package-on-package system including integrated passive components
A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more...
US-7,569,853 Test pads on leads unconnected with die pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test...
US-7,569,499 Semiconductor device made by multiple anneal of stress inducing layer
The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises forming a stress inducing layer over a semiconductor...
US-7,569,486 Spin on glass (SOG) etch improvement method
A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first...
US-7,569,464 Method for manufacturing a semiconductor device having improved across chip implant uniformity
The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack...
US-7,569,309 Gate critical dimension variation by use of ghost features
According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a...
US-7,568,142 Boundary scan path method and system with functional and non-functional scan cell memories
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a...
US-7,567,883 Method and apparatus for synchronizing signals in a testing system
The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal...
US-7,567,624 System and method of communicating using combined signal parameter diversity
A system and method of data communication uses variable transmit antenna delays based on communication signal uplink measurements. The signals for each channel...
US-7,567,620 Data transmission scheme using channel group and DOCSIS implementation thereof
A novel apparatus for and a method of data transmission whereby an input data stream is distributed over a plurality of physical channels within a logical...
US-7,567,255 Color adjustment for clipped pixels
A control module for use in an image display system includes a gain module operable to amplify a signal received by the control module and to communicate an...
US-7,567,138 Single-electron injection/extraction device for a resonant tank circuit and method of operation thereof
A system for reducing phase-noise in a resonant tank circuit. The system includes a single-electron device configured to inject a single electron into the...
US-7,567,134 System and method for synchronizing multiple oscillators
A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference...
US-7,567,116 Voltage converting circuit and battery device
A voltage converting circuit and a battery device, aimed at the problem that the breakdown voltage required for the driving input of the selected switch element...
US-7,567,105 High speed controller area network receiver having improved EMI immunity
A CAN receiver architecture design that provides better immunity against EMI interference than conventional designs is disclosed herein. This CAN receiver...
US-7,566,652 Electrically inactive via for electromigration reliability improvement
A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second...
US-7,566,627 Air gap in integrated circuit inductor fabrication
In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of...
US-7,566,595 Method of making and using guardringed SCR ESD protection cell
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an...
US-7,565,995 Roller wire brake for wire bonding machine
While fabricating a packaged semiconductor chip, a wire is bonded on a chip contact pad using a wire bonding machine. A bond head of the wire bonding machine is...
US-7,565,385 Embedded garbage collection
An electronic system comprises a processor, memory coupled to the processor, and an application programming interface that causes an embedded garbage collection...
US-7,565,125 Telecommunications receiver with automatic gain control
A receiver 30 has an adjustable gain control circuit 32 that provides gain control base on the magnitude of the signal at the input of an analog-to-digital...
US-7,565,111 Single-antenna interference cancellation receiver in time slot communication system
A receiver (MST) for use in a modulated communications system wherein data is communicated in a time-slotted format. The receiver comprises circuitry (22) for...
US-7,564,904 Apparatus for and method of detection of powered devices over a network
A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted...
US-7,564,868 Configuration DSL transceiver
A DSL modem (21) including a configurable digital transceiver (30) is disclosed. The digital transceiver (30) includes a configuration register (43), or other...
US-7,564,826 Apparatus for and method of synchronization and beaconing in a WLAN mesh network
A novel and useful synchronization mechanism that functions to provide a uniform time base for mesh points in a WLAN mesh based network. The invention enables...
US-7,564,725 SRAM bias for read and write
An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines...
US-7,564,391 Sigma delta modulator summing input, reference voltage, and feedback
A multibit sigma delta modulator for conveting an analog input signal (Vin) into a multibit digital output signal is disclosed. In one embodiment, the multibit...
US-7,564,389 Discrete-time, single-amplifier, second-order, delta-sigma analog-to-digital converter and method of operation...
A discrete-time, single-amplifier, second-order, delta-sigma analog-to-digital converter (DT-SADS ADC) and a method of operating the same. The DT-SADS ADC...
US-7,564,077 Performance and area scalable cell architecture technology
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The...
US-7,563,168 Audio effect rendering based on graphic polygons
A method to supply audio effects to video games employs graphics information of sound source objects and sound interacting objects in a real time physical model...
US-7,562,360 Method and system for firmware downloads
A method and system for downloading firmware by a device controller from a data source while connected to a host. The device controller connects to the host and...
US-7,562,333 Method and process for generating an optical proximity correction model based on layout density
A method (300) for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask (310)...
US-7,562,315 Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout
Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage...
US-7,562,259 Distributed depth trace receiver
Input processing limitations may be solved by placing multiple units in series, with each unit recording some portion of the incoming data. This requires the...
US-7,562,170 Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least...
US-7,562,108 High bandwidth high gain receiver equalizer
A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably...
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