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Class AB folded cascode stage and method for low noise, low power,
low-offset operational amplifier
A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and...
Slew-rate controlled pad driver in digital CMOS process using parasitic
A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up...
Shock resistant and mode mixing resistant torsional hinged device
A shock resistant and mode mixing resistant assembly for oscillating a device such as a MEMS mirror around a pivot axis by means of two pairs of piezoelectric...
Integrated high voltage capacitor having capacitance uniformity structures
and a method of manufacture therefor
The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The...
Dual work function CMOS devices utilizing carbide based electrodes
Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low...
Scan sequenced power-on initialization
A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This...
Multi-processor system verification circuitry
A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more...
Method and apparatus for adaptive channel equalization using decision
The equalizer circuit (200) equalizes the channel prior to despreading thereby restoring the orthogonality of signals that typically exists in the forward link...
Silicon mirrors having reduced hinge stress from temperature variations
A device such as a mirror assembly comprises a movable structure (41) having a first movable portion (45) hinged to a frame portion (43) by a first pair of...
Method and apparatus for digital MTS receiver
System and method for an all-digital audio receiver for a BTSC MTS audio signal or other composite signal that is FM modulated. A preferred embodiment comprises...
Drain extended PMOS transistors and methods for making the same
Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation...
High performance charge detection amplifier for CCD image sensors
The CCD charge detection amplifier includes a floating diffusion charge detection node biased from a voltage reference node; a reset device coupled between the...
Apparatus and method for performing a multi-value polling operation in a
JTAG data stream
In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with...
TAP, ST, lockout, and IR SO enable output data control
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves...
Method and apparatus for providing a local oscillator signal
A multi-band RF transceiver (100) includes a single dual band VCO (102) that is used in both transmit and receive modes of operation. The VCO's low band...
Apparatus and method for IF switching in a dual-tuner, dual-IF, HD radio
and FM/AM radio receiver
In a dual-channel HD radio receiver, when the broadband filter channel is compromised, the broadband channel is inactivated and the narrowband channel is...
Active removal of aliasing frequencies in a decimating structure by
changing a decimation ratio in time and space
When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss...
Methods and systems for read-only memory
One embodiment of the present invention relates to a read only memory (ROM) that includes a memory cell pair. The memory cell pair includes a first memory cell...
Technique for CAM width expansion using an external priority encoder
A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment,...
Sloped cantilever beam electrode for a MEMS device
A method of tilting a micromirror includes providing a substrate, a sloped electrode outwardly from the substrate, and a sloped electrode positioning system...
System and method for testing a lighting diode
A system for testing a lighting diode includes one or more nozzles, a probe, and a detector, where the lighting diode is operable to emit light in response to a...
Methods and apparatus to measure a voltage on an integrated circuit
Methods and apparatus to measure a voltage on an integrated circuit are disclosed. An example method to measure a voltage on an integrated circuit provides a...
Gain calibration of a digital controlled oscillator
A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO)...
Class AB output stage and method for providing wide supply voltage range
A class AB output stage includes first (M.sub.P) and a second (M.sub.N) output transistors having sources coupled to first (V.sub.DD) and second reference...
Soft-start circuit and method for power-up of an amplifier circuit
A method and circuit for providing a soft start-up process for an amplifier circuit to reduce or prevent destructive overshoot of an output voltage are provided....
MEMS device wafer-level package
A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of...
Method for reducing dislocation threading using a suppression implant
The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device...
Method for manufacturing a gate sidewall spacer using an energy beam
The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may...
System and method for asynchronous logic synthesis from high-level
A method for generating an equivalent asynchronous handshake circuit from a synchronous description of its intended behavior.
Method for collaboration of issue-resolution by different projects in a
This invention is a toolset upgrading the basic WEBS system update that facilitates tracking design bugs. This invention provides an effective means for...
System and method for producing precision timing signals by controlling
register banks to provide a phase...
Systems and methods are provided for providing precision timing signals. A first register bank, driven by a first clock signal, provides a first delay along a...
Decoding multiple HMM sets using a single sentence grammar
For a given sentence grammar, speech recognizers are often required to decode M sets of HMMs each of which models a specific acoustic environment. In order to...
Stalling CPU pipeline to prevent corruption in trace while maintaining
coherency with asynchronous events
A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out...
Wireless communications device having type-II all-digital phase-locked
System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a...
Low noise high isolation transmit buffer gain control mechanism
A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an...
Methods and apparatus to integrate image rejection into quadrature mixers
Methods and apparatus to integrate image rejection into quadrature mixers are disclosed. A disclosed image-rejection quadrature mixer comprises a quadrature...
Code division multiple access wireless system with closed loop mode using
ninety degree phase rotation and...
A wireless communication system (10). The system comprises a user station (12). The user station comprises despreading circuitry (22) for receiving and...
Apparatus and method for compression of the timing trace stream
In a test and debug system, a plurality of trace streams, including a timing trace stream, are transmitted from the target processing unit to the host processing...
System and method for reducing latency in a memory array decoder circuit
A system and method are disclosed for reducing latency in asserting a word-line for read/write operations of a memory row in a memory array. One embodiment of...
Active float for the dummy bit lines in FeRAM
Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along...
System and method for current overload response with class D topology
A system and method for responding to a current overload condition in a power switch provides a class D topology that applies a current sink or current source to...
Piezoelectric resonator with an efficient all-dielectric Bragg reflector
A piezoelectric resonator with an acoustic Bragg reflector that includes alternating layers of high and low acoustic impedance materials. The high and low...
Method and delay circuit with accurately controlled duty cycle
A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal...
Switching regulator with analog or digital control
A switching regulator provided according to an aspect of the present invention contains uses one or more error samples from prior iterations, in addition to an...
Semiconductor assembly for improved device warpage and solder ball
A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is...
Semiconductor package having a grid array of pin-attached balls
Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top...
Collector tailored structures for integration of binary junction
A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the...
Modifying merged sub-resolution assist features of a photolithographic
Modifying merged sub-resolution assist features includes receiving a mask pattern comprising the merged sub-resolution assist features, where a segmenting...
Skip counter for system timer
A skip counter timing device employing a typical hardware system timer, a skip counter with a skip count register, a signal gate and a hardware system tick...
Bi-modal RF architecture for low power devices
A wireless receiver is provided that includes a component and a power control logic 80. The component is operable to receive a wireless signal and process the...