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Patent # Description
US-7,460,612 Method and apparatus for a fully digital quadrature modulator
A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art...
US-7,460,499 Modulation noise estimation mechanism
An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a...
US-7,460,282 Dynamic pattern generation for optical signal processing
A processor such as a digital signal processor (DSP) is used to dynamically generate patterns and/or sequences of patterns for a spatial light modulator (SLM),...
US-7,460,275 Odd/even error diffusion filter
An error diffusion method and system to ameliorate the effects of data quantization. The error diffusion method is especially well-suited to display systems that...
US-7,460,135 Two dimensional rotation of sub-sampled color space images
In a method and system for controlling rotation of a color image stored as sub-sampled image data in a memory, a controller includes a finite state machine (FSM)...
US-7,460,132 System and method for motion adaptive anti-aliasing
System and method for processing image data containing motion for display on a display device. A preferred embodiment comprises applying a filter to an input...
US-7,459,977 Signal transfer circuit and circuit device using same
A signal transfer circuit appropriate for use in realizing both high circuit stability and high current driving ability is disclosed. Signal transfer circuit A...
US-7,459,926 Scan distributor loading scan paths simultaneous with loading test data
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,459,891 Soft-start circuit and method for low-dropout voltage regulators
A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a...
US-7,459,734 Method for manufacturing and structure for transistors with reduced gate to contact spacing
A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed...
US-7,459,402 Protection layers in micromirror array devices
To protect the structural layers from being eroded in the etching process, a protection layer is deposited on the exposed structural layers of the micromirror....
US-7,459,390 Method for forming ultra thin low leakage multi gate devices
The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment,...
US-7,459,357 Versatile system for cross-lateral junction field effect transistor
The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage,...
US-7,459,339 Flip-chip semiconductor device manufacturing method
The objective of the invention is to provide a semiconductor device manufacturing method that can suppress the formation of voids in the underfill resin and...
US-7,459,333 Method for making a micromirror-based projection system with a programmable control unit for controlling a...
A projection system is disclosed herein. The projection system employs a spatial light modulator comprising an array of individually addressable pixels for...
US-7,459,325 MEMS passivation with transition metals
Organic surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirrors. The binding of these surfactants to the surface is...
US-7,458,691 Holographic combiners for illumination of spatial light modulators in projection systems
Described is an optical device for combining multiple light sources in an optical projection system. One embodiment of the optical device includes at least two...
US-7,458,058 Verifying a process margin of a mask pattern using intermediate stage models
Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified...
US-7,458,007 Error correction structures and methods
A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency....
US-7,457,993 Error free dynamic rate change in a digital subscriber line DSL with constant delay
A method for changing the data rate over an interleaved latency path overcomes shortfalls of the ADSL2 seamless rate adaptation (SRA) and dynamic rate...
US-7,457,986 Apparatus and method for using variable end state delay to optimize JTAG transactions
In a JTAG test and debug environment, the parameters that are accessed by command include a delay parameter. The delay parameter prevents the subsequent command...
US-7,457,973 System and method for prioritizing data transmission and transmitting scheduled wake-up times to network...
A new system and method is described, utilizing a scheduler based on a transmission time calculation and prioritizing algorithm. The system utilizes a Schedule...
US-7,457,739 Read FIFO scheduling for multiple streams while maintaining coherency
A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out...
US-7,457,625 Wirelessly-linked, distributed resource control to support wireless communication in non-exclusive spectrum
Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum...
US-7,457,381 Spread spectrum multipath combination
Multipath relative channel estimations for weighting maximal ratio combining of RAKE detectors in wireless communication systems uses maximal eigenvectors of...
US-7,457,369 Scalable gain training generator, method of gain training and MIMO communication system employing the generator...
The present invention provides a gain training generator for use with a multiple-input, multiple-output (MIMO) transmitter employing N transmit antennas where N...
US-7,457,362 Loop deblock filtering of block coded video in a very long instruction word processor
This invention is applicable to filtering block artifacts of macroblock and block oriented video compression. This invention computes all possible filter results...
US-7,457,258 Tunable filter to facilitate communications
Systems and methods are described herein for changing the frequency response of a filter, such as a hybrid circuit. One or more tunable components are adjustable...
US-7,457,232 Frequency switched preamble design to minimize channel estimation time in MIMO communications systems
A preamble frequency switching design technique for frequency switching the training symbols within the preamble associated with a MIMO communication system...
US-7,457,173 Area efficient differential EEPROM cell with improved data retention and read/write endurance
An electrically erasable programmable read only memory (EEPROM) (500) is disclosed having improved data retention and read/write endurance. The EEPROM also lacks...
US-7,457,137 Output sensor circuit for power supply regulation with main and switched outputs
A sense circuit is provided connected to a control loop of a circuit having an output. The sense circuit receives a signal derived from the output of the circuit...
US-7,457,023 Manufacturing a mirror plate or other operational structure having superior flatness by laser milling for use...
A multilevel mirror plate suitable for use with a torsional hinged mirror assembly is laser milled to provide a more effective truss structure in less time and...
US-7,456,477 Electrostatic discharge device and method
The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events...
US-7,456,070 Method of fabricating a bipolar transistor with high breakdown voltage collector
A method of fabricating a transistor that includes a doped buried region within a semiconductor body. The doped buried region includes a portion having a first...
US-7,455,448 Rapid thermal anneal equipment and method using sichrome film
A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet...
US-7,454,946 Systems and methods of self test for a slowly varying sensor
Systems, methods and circuits for implementing a self test in a slowly varying sensor. In one particular case, a circuit is provided that includes two filters...
US-7,454,677 Two boundary scan cell switches controlling input to output buffer
A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is...
US-7,454,535 Bidirectional data repeater switch
A bidirectional repeater and data multiplexer for serial data has A-side I2C port devices A1-A4 coupled to comparators 302-308 and pulldowns to ground 316-322....
US-7,454,452 Fast fourier transform operation with reduced cache penalty
A data processing apparatus having data cache performs an N-point radix-R Fast Fourier Transform. If the data set is smaller than the data cache, the data...
US-7,453,930 Method and system of tone ordering for discrete multi-tone systems with tone grouping
The present disclosure describes a method and system of tone ordering for discrete multi-tone (DMT) systems with tone grouping. Some illustrative embodiments may...
US-7,453,889 Interoperability of ADPCM encoded voice communications
Providing interoperability on a voice communication network by detecting incompatible bit packing payload formats of ADPCM encoded voice data signals in an...
US-7,453,843 Wireless bandwidth aggregator
Wireless communications networks offer rapid installation and good mobility in return for relatively low data bandwidth. The present invention makes use of any...
US-7,453,743 Static random access memory device having reduced leakage current during active mode and a method of operating...
An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row...
US-7,453,659 Circuit and method for write current driver
System and method for write current drivers for inductive heads used in mass storage drives. A preferred embodiment comprises a write current circuit coupled to...
US-7,453,525 Motion detector for a video display system
Systems and methods are provided for detecting motion within a composite video signal. A first chroma difference element compares an in-phase chroma component of...
US-7,453,319 Multi-path common mode feedback for high speed multi-stage amplifiers
The invention includes methods and systems for providing a multi-path common mode feedback loop in an amplifier system. Embodiments include techniques for...
US-7,453,283 LVDS input circuit with connection to input of output driver
First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an...
US-7,453,142 System and method for implementing transformer on package substrate
A transformer system includes a package substrate having a surface. A plurality of electrically conductive pads are arranged in spaced apart relationship...
US-7,452,818 Method for selectively etching portions of a layer of material based upon a density or size of semiconductor...
The disclosure provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming semiconductor features (405, 410, 415,...
US-7,452,799 Ball film for integrated circuit fabrication and testing
According to one embodiment of the invention, a method of fabricating ball grid array packages includes providing a substrate, providing a ball film that...
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