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Patent # Description
US-7,508,027 Single-poly EPROM device and method of manufacturing
The invention relates to a single-poly EPROM comprising a source, a drain, a control gate, a floating gate and an additional gate. The control gate is positioned...
US-7,508,013 Versatile system for cross-lateral junction field effect transistor
The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage,...
US-7,507,605 Low cost lead-free preplated leadframe having improved adhesion and solderability
A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack...
US-7,506,238 Simplified LDPC encoding for digital communications
Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix...
US-7,506,131 Reformat logic to translate between a virtual address and a compressed physical address
In some embodiments, reformat logic comprises a plurality of registers and translation logic that accesses the registers. The translation logic receives a memory...
US-7,505,526 Methods and apparatus for self-inverting turbo code interleaving with high separation and dispersion
The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods...
US-7,505,525 Methods and apparatus for self-inverting turbo code interleaving with high separation and dispersion
The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods...
US-7,504,977 Hybrid delta-sigma/SAR analog to digital converter and methods for using such
Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first...
US-7,504,895 Multi-phase interleaved oscillator
An oscillator for synchronizing and controlling a multi-phase, interleaved power supply system that has a plurality of power sources. The oscillator includes a...
US-7,504,857 Functional cells for automated I/O timing characterization of an integrated circuit
Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive...
US-7,504,716 Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
A semiconductor device comprising a semiconductor chip (101) assembled on a first copper cuboid (110); the cuboid has sides of a height (111). The device further...
US-7,504,713 Plastic semiconductor packages having improved metal land-locking features
A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent...
US-7,504,339 Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits
A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a...
US-7,504,329 Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET
Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and...
US-7,504,283 Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
A semiconductor system having a substrate (101) including a rigid insulating interposer (110) with a high modulus and a top (140) and a bottom (150) low-modulus...
US-7,502,727 Tracing user change of program counter during stop event
This invention tracks emulation changes in the program counter of the central processing unit of a data processor during emulation halt. The sequence includes:...
US-7,502,591 Multi-mode radio piconet/scatternet
A communication system 100 allows for heterogeneous piconets/scattenets 100 where in multiple modes 110, 112 of transmission, one of Bluetooth 110 and one or...
US-7,502,337 Intelligent voice network monitoring using echo cancellation statistics
Monitoring voice quality passively using line echo cancellation data across a telecommunications network and reporting monitoring data to a central network...
US-7,502,247 Memory array with a delayed wordline boost
Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets...
US-7,502,155 Antireflective coating for semiconductor devices and method for the same
According to one embodiment of the present invention, a semiconductor device includes a first layer of dielectric material disposed upon an upper surface of a...
US-7,502,076 Method and apparatus for a digital display
A method and apparatus for a digital video display. A digital display device receives an analog signal representing an image formed of pixels in video lines and...
US-7,502,075 Video processing subsystem architecture
A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The...
US-7,501,981 Methods and apparatus to detect and correct integrity failures in satellite positioning system receivers
Methods and apparatus to detect integrity failures in satellite position system (SPS) receivers are disclosed. An example method comprises estimating a position...
US-7,501,970 Digital to analog converter architecture and method having low switch count and small output impedance
A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to...
US-7,501,965 Correcting for errors that cause generated digital codes to deviate from expected values in an ADC
Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored...
US-7,501,964 Entropy coding for digital codecs
A method and systems are provided for efficiently implementing content adaptive variable length coding on a modern processor. Some embodiments comprise encoding...
US-7,501,324 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-7,500,130 Cycle-accurate real-time clocks and methods to operate the same
Cycle-accurate real-time clocks and methods to operate the same are disclosed. An example real-time clock comprises a first counter to count cycles of a...
US-7,500,085 Identifying code for compilation
A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further...
US-7,499,848 Scripting support for an emulator
An emulation system that allows a user to create a script is provided. The emulation system emulates a handheld computing device, such as a calculator, on an...
US-7,499,505 Trellis decoding with finite constellation boundaries
System and method for improving trellis decoding in communications systems with finite constellation boundaries. A preferred embodiment for a received point of a...
US-7,499,487 System and method to mitigate interference in DSL systems
Systems and methods are disclosed for determining mitigating noise in multi-pair communication system. A receiver coordinated system can include an error...
US-7,499,368 Variable clocking read capture for double data rate memory devices
A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device...
US-7,499,354 Method for testing transistors having an active region that is common with other transistors and a testing...
The present invention provides a method for testing an electrical property of one or more functionally separate transistors located within an active region that...
US-7,499,065 Asymmetrical switching delay compensation in display systems
A method and apparatus of the present invention is particularly for use in display systems having spatial light modulators in which the pixels present...
US-7,499,030 Graphics initialization for wireless display devices
A method of optimizing bandwidth of a wireless link between a display device and an image data player. The display device is configured with one or more features...
US-7,498,890 Continuous reversible gear shifting mechanism
A novel gear shifting mechanism operative to adjust the loop gain of a phase locked loop (PLL) circuit in a continuous and reversible manner. The loop gain can...
US-7,498,879 Summing comparator for higher order class D amplifiers
The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the...
US-7,498,870 Adaptive voltage control for performance and energy optimization
A device for adaptively controlling a voltage supplied to circuitry in substantially close proximity to the device, comprising a processing module, a first...
US-7,498,862 Switch for handling terminal voltages exceeding control voltage
A switch provided between a first terminal and a second terminal with a varying cross terminal voltage. The switch contains two transistors, with the source...
US-7,498,690 System and method for regulating power in a multiple-output switching converter
A system and method is provided for supplying power to multiple outputs in a switching converter. One embodiment of the present invention includes a ...
US-7,498,654 Transistor apparatus
A transistor apparatus includes a silicon substrate and a barrier structure extending substantially from generally adjacent the silicon substrate to a locus...
US-7,498,652 Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure...
US-7,498,648 Mirror-based projection system with a programmable control unit for controlling a spatial light modulator
A projection system is disclosed herein. The projection system employs a spatial light modulator comprising an array of individually addressable pixels for...
US-7,498,639 Integrated BiCMOS semiconductor circuit
An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor...
US-7,498,264 Method to obtain fully silicided poly gate
The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material 160 over gate...
US-7,498,219 Methods for reducing capacitor dielectric absorption and voltage coefficient
Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through...
US-7,498,203 Thermally enhanced BGA package with ground ring
The invention provides thermally enhanced BGAs and methods for their fabrication with a ground ring suitable for operably coupling to either the frontside or...
US-7,496,930 Accessing device driver memory in programming language representation
In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application...
US-7,496,822 Apparatus and method for responding to data retention loss in a non-volatile memory unit using error checking...
In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking...
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