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Patent # Description
US-7,443,217 Circuit and method to balance delays through true and complement phases of differential and complementary drivers
A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device...
US-7,443,189 Method to detect and predict metal silicide defects in a microelectronic device during the manufacture of an...
The present teachings provide methods for detection of metal silicide defects in a microelectronic device. In an exemplary embodiment, a portion of a...
US-7,443,140 Method and apparatus for operating a battery to avoid damage and maximize use of battery capacity by...
A method for terminating battery discharge to avoid battery damage and maximize battery usage includes the steps of: (a) determining battery capacity; (b)...
US-7,443,020 Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit
Dummy stacks, each providing a common point of connectivity potentially across all metal layers, are incorporated along with the functional block in an...
US-7,443,007 Trench isolation structure having an implanted buffer layer
The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the...
US-7,442,972 Semiconductor device and inspection method thereof
A semiconductor device is disclosed. The device has a photodiode isolated by element isolating regions (Ia, 14a, 14b) characterized by the following facts: on...
US-7,442,626 Rectangular contact used as a low voltage fuse element
A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse...
US-7,442,597 Systems and methods that selectively modify liner induced stress
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a...
US-7,442,412 Hydrophobic coating for oxide surfaces
The disclosure relates to hydrophobic coatings for oxidized surfaces and methods of producing the same. Such coatings may be produced by applying a compound of...
US-7,441,218 Contact resistance and capacitance for semiconductor devices
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design....
US-7,441,170 External scan circuitry connected to leads extending from core circuitry
An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test...
US-7,440,511 Transmit filter
A transmit filter (100) receives a stream of data symbols (DT_TX) at a baseband symbol clock rate. An available clock (FREF) is used to generate sample points...
US-7,440,491 Ultra-wideband communications system devices
System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment...
US-7,440,484 Reduced hopping sequences for a frequency hopping system
A frequency hopping system such as a Bluetooth system (300) can reduce the number of RF channels it hops during a normal hopping sequence cycle providing for a...
US-7,439,888 Method for digitally representing an integral non-linearity response for a device
A method digitally representing an integral non-linearity response for a device includes: (a) In no particular order: (1) Identifying locations of significant...
US-7,439,817 Frequency tuning range extension and modulation resolution enhancement of a digitally controlled oscillator
A novel apparatus and method of extending the frequency tuning range and improving the modulation resolution of an RF digitally controlled oscillator (DCO). In...
US-7,439,796 Current mirror with circuitry that allows for over voltage stress testing
A current mirror circuit that allows for over voltage stress testing includes: a first transistor; a second transistor having a gate coupled to a gate of the...
US-7,439,612 Integrated circuit package structure with gap through lead bar between a die edge and an attachment point...
In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars...
US-7,439,106 Gate CD trimming beyond photolithography
A semiconductor device is fabricated with a selected critical dimension. A gate dielectric layer is formed over a semiconductor body. A gate layer comprised of a...
US-7,437,639 Response bits as stimulus in subdivided scan path delay test
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and...
US-7,437,623 Apparatus and method for performing speculative reads from a scan control unit using FIFO buffer units
A method for debugging a target processor is provided that includes storing a plurality of data values to be sent to the target processor in a first-in first-out...
US-7,437,262 System and method for testing a device
A system for testing a device includes a processor that operates to execute instructions, where the instructions are used to test a device. The processor also...
US-7,436,850 Ultra-wideband (UWB) transparent bridge
System and method for transparently attaching wireless peripherals to a computer using an UWB wireless network. A preferred embodiment comprises an interface...
US-7,436,701 Single poly EPROM device with double control gates to prevent unintentionally charging/discharging
A single poly EPROM comprises a floating gate (10), a control gate (12), a source (16) and a drain (18). The control gate (12) is positioned laterally of a...
US-7,436,573 Electrical connections in microelectromechanical devices
A micromirror device and a method of making the same are disclosed herein. The micromirror device comprises a mirror plate, hinge, and post each having an...
US-7,436,572 Micromirrors and hinge structures for micromirror arrays in projection displays
A spatial light modulator is disclosed, along with methods for making such a modulator. The spatial light modulator comprises an array of micromirrors each...
US-7,436,328 Video coding with start code emulation prevention
A low-complexity method for prevention of H.264 start code emulation by bit-handling routines with additional functionality. The low-complexity is achieved by...
US-7,436,281 Method to improve inductance with a high-permeability slotted plate core in an integrated circuit
An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed...
US-7,436,263 Apparatus and method for presenting a modulated output signal at an output locus
An apparatus that presents an output signal that is modulated by input signal includes: (a) A signal source providing a signal at a reference frequency. (b) A...
US-7,436,238 Integrated voltage switching circuit
An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum...
US-7,436,168 Test error detection method and system
According to one embodiment, a method of test error detection for a wafer having a plurality of rows of integrated circuit (IC) chips is provided. The method...
US-7,436,003 Vertical thyristor for ESD protection and a method of fabricating a vertical thyristor for ESD protection
A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and...
US-7,435,672 Metal-germanium physical vapor deposition for semiconductor device defect reduction
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by...
US-7,435,659 Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a...
The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor...
US-7,435,651 Method to obtain uniform nitrogen profile in gate dielectrics
The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160...
US-7,435,638 Dual poly deposition and through gate oxide implants
Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and...
US-7,434,946 Illumination system with integrated heat dissipation device for use in display systems employing spatial light...
Disclosed herein is an illumination system for use in display systems employing spatial light modulators. The illumination system comprises a fastening mechanism...
US-7,434,029 Inter-processor control
A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and...
US-7,434,021 Memory allocation in a multi-processor system
A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor...
US-7,433,984 Time-based weighted round robin arbiter
A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the...
US-7,432,841 Delta-sigma analog-to-digital converter with pipelined multi-bit quantization
A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A...
US-7,432,572 Method for stripping sacrificial layer in MEMS assembly
The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror...
US-7,432,566 Method and system for forming dual work function gate electrodes in a semiconductor device
A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly...
US-7,430,141 Method and apparatus for memory data deskewing
A memory interface (20) for receiving memory signals individually synchronizes data signals to a delayed strobe signal in order to reduce the spread of the data...
US-7,430,072 System and method for increasing image quality in a display system
System and method for maximizing image quality by eliminating vias on a reflective surface. A preferred embodiment comprises depositing a first portion of a...
US-7,429,895 Systems and methods for drift compensation in a control circuit
Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes...
US-7,429,524 Transistor design self-aligned to contact
The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one...
US-7,429,517 CMOS transistor using high stress liner layer
A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor...
US-7,428,719 Layout of network using parallel and series elements
Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically...
US-7,428,666 Apparatus and method for trace stream identification of a pipeline flattener secondary code flush following a...
When an INTERRUPT SERVICE ROUTINE (SECONDARY) CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a...
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