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Patent # Description
US-7,483,003 Drive circuit and display system with said drive circuit
The objective of this invention is to provide a drive circuit and display system that can efficiently transfer prescribed information indicating an abnormality...
US-7,482,883 Gain normalization of a digitally controlled oscillator in an all digital phase locked loop based transmitter
A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is...
US-7,482,785 Transponder with oscillator peak voltage limit
A transponder device having an LC oscillator circuit, an energy storage capacitor and an integrated transponder circuit powered by energy from the storage...
US-7,482,214 Transistor design and layout for performance improvement with strain
The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both...
US-7,480,488 Providing optimal uplink data rates to mobile stations when mobile networks send parameters controlling the...
The uplink data rate is dynamically adjusted in a mobile station according to the mobile station's ability to meet QoS (quality of service) requirements of...
US-7,480,089 Micromirror system with electrothermal actuator mechanism
The disclosed embodiments combine an electrothermal actuator system with an electrostatic attraction system, in order to orient bistable micromirrors in digital...
US-7,479,915 Comparator architecture
A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in...
US-7,479,912 Low-power high-performance audio DAC system including internal oscillator, FIFO memory, and ASRC
A low-power data conversion system for converting a serial digital data input signal (DIN) to an analog output signal (Vout) by generating the serial digital...
US-7,479,816 Generating multiple delayed signals of different phases from a reference signal using delay locked loop (DLL)
A delay locked loop (DLL) circuit in which situations of lock to multiple periods of a reference signal is determined by a lock detector using dummy delay...
US-7,479,770 System and method for driving a power field-effect transistor (FET)
A system and method is provided for driving a power field-effect transistor (FET). In one embodiment, a system comprises a control circuit that generates a...
US-7,479,675 Solid-state image pickup device and manufacturing method thereof
A solid-state image pickup device that can suppress the dark current with respect to the photo-electrons overflowing from the photodiode, as well as its...
US-7,479,668 Source/drain extension implant process for use with short time anneals
The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate...
US-7,478,353 Non-uniform decoupling capacitor distribution for uniform noise reduction across chip
An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level...
US-7,477,875 Built in loop back self test in design or on test board for transceivers
In a method and system for testing a transceiver communication device operating in a test mode, a transmitter output signal generated by a transmitter is...
US-7,477,846 Method of reducing control packet transmission rate for an optical wireless link
A method that does not rely on signal strength for detecting the presence of a broken optical wireless link. The method controls the packet transfer rate in a...
US-7,477,778 Sequential color reproduction method
An improved color processing method for use in imaging systems transforms the input color image components into an output set of color image components, at least...
US-7,477,714 Phase adjusting circuit for minimized irregularities at phase steps
An integrated phase adjusting circuit (12) for the generation of a clock output signal (CLK.sub.out) with a phase intermediate the phases of first and second...
US-7,477,551 Systems and methods for reading data from a memory array
One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that...
US-7,477,219 Micro-mirror and method
According to one embodiment of the present invention a method of reflecting light is disclosed including providing an element having a surface having an edge on...
US-7,477,158 Method and apparatus for brightness control of indication lights
A method for gradually increasing the brightness of an indicator light. An activation signal is received indicating that the indicator light should be lit. Upon...
US-7,477,090 Circuit characteristics controller
A circuit characteristics controller (10) changes the supply voltage to circuit (12) on the basis of the characteristics of at least one transistor in circuit...
US-7,476,976 Flip chip package with advanced electrical and thermal properties for high current designs
A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the...
US-7,476,961 Method and apparatus for forming a DMD window frame with molded glass
An improved method for fabricating a window frame/window piece assembly is disclosed in this application. A window frame having an opening in its inner portion...
US-7,476,960 System and method for improved auto-boating
According to one embodiment of the invention, a method for auto-boating includes supporting a tape substrate having first and second end portions on a boat,...
US-7,476,949 Low compressive TiN.sub.x materials and methods of making the same
Disclosed herein is a microelectromechanical device having a structural layer composed of a low stress TiN.sub.x layer and a method of making the same.
US-7,476,602 N.sub.2 based plasma treatment for enhanced sidewall smoothing and pore sealing porous low-k dielectric films
A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k...
US-7,476,597 Methods and systems for laser assisted wirebonding
The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for...
US-7,475,802 Method for low loop wire bonding
A method is provided for low loop wire bonding. The method includes forming a first bond between a first bonding ball disposed at an end of a first wire and a...
US-7,475,313 Unique pBIST features for advanced memory testing
This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the...
US-7,475,231 Loop detection and capture in the instruction queue
A system and a method to identify a conditional branch instruction having a program counter and a target address, and increment a loop count each time the...
US-7,475,172 Progressive extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least...
US-7,474,688 System and method for detecting multiple direct sequence spread spectrum signals using a multi-mode searcher
System and method for detecting multiple direct sequence spread spectrum signals using a multi-mode searcher. A preferred embodiment comprises the specification...
US-7,474,686 Wireless personal area networks with rotation of frequency hopping sequences
Wireless personal area networks with frequency hopping and rotation of the frequency hopping sequences. In one embodiment, a method of wireless communication is...
US-7,474,582 Systems and methods for managing power
One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first...
US-7,474,345 System and method to facilitate time domain sampling for solid state imager
A time domain sampling technique for a CMOS imager enables a wide dynamic range and flexibility by employing up to two-degrees of freedom during such sampling....
US-7,474,234 Serial interface circuit for a single logic input pin of an electronic system
A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied...
US-7,474,126 Parallel bipolar logic devices and methods for using such
Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the present invention provide parallel differential logic...
US-7,474,112 Method and apparatus for non-invasively testing integrated circuits
The preferred embodiments of the present invention provide non-invasive approaches of testing ICs that use photon emission from semiconductor devices to provide...
US-7,474,089 Contact mechanism cleaning
One embodiment of the present invention includes a method for reactively cleaning a contact mechanism. The method includes measuring contact resistance (CRES)...
US-7,473,578 Encapsulation for particle entrapment
A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents...
US-7,471,745 Method and apparatus for channel quality metric generation within a packet-based multicarrier modulation...
A communication system disclosed herein includes a channel quality estimation module that determines the channel quality metric utilizing the preamble portion of...
US-7,471,570 Embedded EEPROM array techniques for higher density
An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM...
US-7,471,536 Match mismatch emulation scheme for an addressed location in a CAM
A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are...
US-7,471,273 Bit segment timing organization providing flexible bit segment lengths
Disclosed are reset techniques for a spatial light modulator, and related system for displaying an image. The systems and methods have pixels that are loaded...
US-7,471,222 Providing input signal through a sample and hold circuit with reduced distortion
According to an aspect of the present invention, samples of an input signal are provided with reduced distortion, when the input signal is received from a lead...
US-7,471,150 Class AB folded cascode stage and method for low noise, low power, low-offset operational amplifier
A class AB folded cascode circuit includes a differential current follower having first and second cascode transistors with emitters connected to first and...
US-7,471,111 Slew-rate controlled pad driver in digital CMOS process using parasitic device cap
A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up...
US-7,471,032 Shock resistant and mode mixing resistant torsional hinged device
A shock resistant and mode mixing resistant assembly for oscillating a device such as a MEMS mirror around a pivot axis by means of two pairs of piezoelectric...
US-7,470,991 Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor
The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The...
US-7,470,577 Dual work function CMOS devices utilizing carbide based electrodes
Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low...
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