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Protocol replay system
An expert protocol analyzer, which records a protocol exchange between two or more hardware devices on a network or software modules in a multiprogramming...
Timing recovery of PAM signals using baud rate interpolation
A timing recovery method enables interpolation of PAM signals sampled at baud rate. The method exploits the structure of the PAM signal and also the smoothness...
System and method of removing discrete spurious signals in cable broadband
and other RF environments
A system and method of removing discrete spurious signals in cable broadband environments as well as in other RF environments employs either non-decision...
Time-to-digital converter with non-inverting buffers, transmission gates
and non-linearity corrector, SOC...
A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity...
Detecting amplifier out-of-range conditions
Out-of-range conditions are detected in amplifier CMOS or BiCMOS circuitry that includes a control transistor (M.sub.S) connected in series with a cascode...
Low power control mode for power supply
Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present...
Drain-extended MOS transistors and methods for making the same
Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer...
Guardringed SCR ESD protection
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an...
Method to improve drive current by increasing the effective area of an
The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100...
Semiconductor memory device equipped with error correction circuit
The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that...
Scheduling system and method
Photolithography operation in a wafer fab using relative weightings of work in progress to iteratively schedule wafers.
Video decoder with different signal types processed by common
A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also...
Signal-to-noise ratio when using fewer bits than the number of output bits
of an analog to digital converter
Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of...
All-digital phase-locked loop for a digital pulse-width modulator
A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a ...
Recovery from clipping events in a class D amplifier
A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20),...
Apparatus and method for generating pulses
An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for...
Integrated driver circuit structure
An integrated circuit driver structure, comprising an amplifier, a current mirror block and an external current set resistor, is provided that is digitally...
Method for etching a substrate and a device formed using the method
The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and...
Minimizing resist poisoning in the manufacture of semiconductor devices
The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The...
Modifying sub-resolution assist features according to rule-based and
Modifying sub-resolution assist features includes receiving a mask pattern for a photolithographic mask. The mask pattern includes main features, and the...
Method and apparatus for performing multi-site integrated circuit device
Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the...
Method for adjusting the resonant frequency of an oscillating device
A method for increasing the resonant frequency of a torsional hinged device having a reduced attaching area between the torsional hinges and the supporting...
Method of monitoring the light integrator of a photolithography system
A method of monitoring a light integrator of a photolithography system, wherein the photolithography system comprises a light source for illuminating different...
Sigma-delta modulator using a passive filter
A sigma-delta modulator includes a discrete time circuit that receives a digital feedback signal and an input signal, where the input signal includes information...
Apparatus and method for comparison of a plurality of analog signals with
In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In...
Providing optimal supply voltage to integrated circuits
A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the...
Triangulating phase interpolator
There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current...
System and method for early qualification of semiconductor devices
According to one embodiment of the invention, a method for early qualification of semiconductor device includes performing initial testing on a semiconductor...
Battery protecting circuit
This invention provides a battery protecting circuit where even if the battery voltage falls nearly to zero volts due to overdischarge or the like while an NMOS...
Bi-layer etch stop process for defect reduction and via stress migration
A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric...
Integrated circuits with composite gate dielectric
CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a...
On chip heating for electrical trimming of polysilicon and
polysilicon-silicon-germanium resistors and...
An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing...
Multi-step process for patterning a metal gate electrode
The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method...
Method for manufacturing a semiconductor device having silicided regions
The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the...
Method for manufacturing a semiconductor device containing metal silicide
The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for...
Method and forming a micromirror array device with a small pitch size
A spatial light modulator is disclosed, along with a method for making such a modulator that comprises an array of micromirror devices. The center-to-center...
Sequential scan based techniques to test interface between modules
designed to operate at different frequencies
According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan...
Controller receiving combined TMS/TDI and suppyling separate TMS and TDI
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
System and method for selecting precursor equalizer coefficients and
serializer deserializer incorporating the same
In one aspect, the present invention provides a system and method for selecting precursor equalizer coefficients and a serializer deserializer (SERDES)...
Method and system for data transfer
The objective of the invention is to provide a type of data transfer system for generating plural timing signals, etc. for any device. Data transfer system A...
Extended range delta-sigma modulator and delta-sigma power converter
Devices, systems, and methods for providing delta-sigma modulation in conjunction with analog-to-digital or digital-to-analog signal conversion are disclosed....
Pre-charge systems and methods for ADC input sampling
The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are...
Phase-locked loop with a digital calibration loop and an analog
A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a...
Hysteretic DC/DC converter
A hysteretic DC/DC converter is proposed that operates at a high switching frequency without producing undesired pulse bursts at the output. The converter has a...
Method for quantifying over-etch of a conductive feature
The invention provides a method for quantifying over-etch of a conductive feature. In one embodiment, this method includes forming a conductive feature over a...
Integrated circuit having electrically isolatable test circuitry
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test....
Multimode, multiline data transfer system and method of operating the same
Multimode, multiline data transfer systems and methods of operating the same. In one embodiment, one system includes: (1) a bus interface for a bus, the bus...
Flexible initialization method for DSL communication systems
A communication system 10 initialized using an iterative training portion is disclosed. The communication system 10 comprises a first transceiver 12 operable to...
Transmitter and receiver for use with an orthogonal frequency division
The present invention discloses a transmitter and receiver for use with an orthogonal frequency division multiplexing (OFDM) communications system. In one...
Optical disk data processing device and data recording/reproduction device
having interruption and restart of...
The objective of this invention is to provide a type of data processing device and a type of data recording/reproduction device that can restart data write...