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Patent # Description
US-7,437,639 Response bits as stimulus in subdivided scan path delay test
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and...
US-7,437,623 Apparatus and method for performing speculative reads from a scan control unit using FIFO buffer units
A method for debugging a target processor is provided that includes storing a plurality of data values to be sent to the target processor in a first-in first-out...
US-7,437,262 System and method for testing a device
A system for testing a device includes a processor that operates to execute instructions, where the instructions are used to test a device. The processor also...
US-7,436,850 Ultra-wideband (UWB) transparent bridge
System and method for transparently attaching wireless peripherals to a computer using an UWB wireless network. A preferred embodiment comprises an interface...
US-7,436,701 Single poly EPROM device with double control gates to prevent unintentionally charging/discharging
A single poly EPROM comprises a floating gate (10), a control gate (12), a source (16) and a drain (18). The control gate (12) is positioned laterally of a...
US-7,436,573 Electrical connections in microelectromechanical devices
A micromirror device and a method of making the same are disclosed herein. The micromirror device comprises a mirror plate, hinge, and post each having an...
US-7,436,572 Micromirrors and hinge structures for micromirror arrays in projection displays
A spatial light modulator is disclosed, along with methods for making such a modulator. The spatial light modulator comprises an array of micromirrors each...
US-7,436,328 Video coding with start code emulation prevention
A low-complexity method for prevention of H.264 start code emulation by bit-handling routines with additional functionality. The low-complexity is achieved by...
US-7,436,281 Method to improve inductance with a high-permeability slotted plate core in an integrated circuit
An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed...
US-7,436,263 Apparatus and method for presenting a modulated output signal at an output locus
An apparatus that presents an output signal that is modulated by input signal includes: (a) A signal source providing a signal at a reference frequency. (b) A...
US-7,436,238 Integrated voltage switching circuit
An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum...
US-7,436,168 Test error detection method and system
According to one embodiment, a method of test error detection for a wafer having a plurality of rows of integrated circuit (IC) chips is provided. The method...
US-7,436,003 Vertical thyristor for ESD protection and a method of fabricating a vertical thyristor for ESD protection
A vertical thyristor for ESD protection comprises an anode (10), a cathode (16), a first gate electrode (12) and a second gate electrode (14). The first (12) and...
US-7,435,672 Metal-germanium physical vapor deposition for semiconductor device defect reduction
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by...
US-7,435,659 Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a...
The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor...
US-7,435,651 Method to obtain uniform nitrogen profile in gate dielectrics
The present invention, in one aspect, provides a method of manufacturing a microelectronics device 100 that includes depositing a first gate dielectric layer 160...
US-7,435,638 Dual poly deposition and through gate oxide implants
Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and...
US-7,434,946 Illumination system with integrated heat dissipation device for use in display systems employing spatial light...
Disclosed herein is an illumination system for use in display systems employing spatial light modulators. The illumination system comprises a fastening mechanism...
US-7,434,029 Inter-processor control
A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and...
US-7,434,021 Memory allocation in a multi-processor system
A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor...
US-7,433,984 Time-based weighted round robin arbiter
A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the...
US-7,432,841 Delta-sigma analog-to-digital converter with pipelined multi-bit quantization
A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A...
US-7,432,572 Method for stripping sacrificial layer in MEMS assembly
The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror...
US-7,432,566 Method and system for forming dual work function gate electrodes in a semiconductor device
A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly...
US-7,430,141 Method and apparatus for memory data deskewing
A memory interface (20) for receiving memory signals individually synchronizes data signals to a delayed strobe signal in order to reduce the spread of the data...
US-7,430,072 System and method for increasing image quality in a display system
System and method for maximizing image quality by eliminating vias on a reflective surface. A preferred embodiment comprises depositing a first portion of a...
US-7,429,895 Systems and methods for drift compensation in a control circuit
Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes...
US-7,429,524 Transistor design self-aligned to contact
The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one...
US-7,429,517 CMOS transistor using high stress liner layer
A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor...
US-7,428,719 Layout of network using parallel and series elements
Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically...
US-7,428,666 Apparatus and method for trace stream identification of a pipeline flattener secondary code flush following a...
When an INTERRUPT SERVICE ROUTINE (SECONDARY) CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a...
US-7,428,664 Protocol replay system
An expert protocol analyzer, which records a protocol exchange between two or more hardware devices on a network or software modules in a multiprogramming...
US-7,428,282 Timing recovery of PAM signals using baud rate interpolation
A timing recovery method enables interpolation of PAM signals sampled at baud rate. The method exploits the structure of the PAM signal and also the smoothness...
US-7,428,281 System and method of removing discrete spurious signals in cable broadband and other RF environments
A system and method of removing discrete spurious signals in cable broadband environments as well as in other RF environments employs either non-decision...
US-7,427,940 Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, SOC...
A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity...
US-7,427,898 Detecting amplifier out-of-range conditions
Out-of-range conditions are detected in amplifier CMOS or BiCMOS circuitry that includes a control transistor (M.sub.S) connected in series with a cascode...
US-7,427,852 Low power control mode for power supply
Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present...
US-7,427,795 Drain-extended MOS transistors and methods for making the same
Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer...
US-7,427,787 Guardringed SCR ESD protection
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an...
US-7,427,543 Method to improve drive current by increasing the effective area of an electrode
The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100...
US-7,426,683 Semiconductor memory device equipped with error correction circuit
The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that...
US-7,426,419 Scheduling system and method
Photolithography operation in a wafer fab using relative weightings of work in progress to iteratively schedule wafers.
US-7,425,994 Video decoder with different signal types processed by common analog-to-digital converter
A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also...
US-7,425,911 Signal-to-noise ratio when using fewer bits than the number of output bits of an analog to digital converter
Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of...
US-7,425,874 All-digital phase-locked loop for a digital pulse-width modulator
A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a ...
US-7,425,864 Recovery from clipping events in a class D amplifier
A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20),...
US-7,425,859 Apparatus and method for generating pulses
An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for...
US-7,425,848 Integrated driver circuit structure
An integrated circuit driver structure, comprising an amplifier, a current mirror block and an external current set resistor, is provided that is digitally...
US-7,425,512 Method for etching a substrate and a device formed using the method
The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and...
US-7,425,502 Minimizing resist poisoning in the manufacture of semiconductor devices
The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The...
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