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Patent # Description
US-7,433,984 Time-based weighted round robin arbiter
A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the...
US-7,432,841 Delta-sigma analog-to-digital converter with pipelined multi-bit quantization
A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A...
US-7,432,572 Method for stripping sacrificial layer in MEMS assembly
The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror...
US-7,432,566 Method and system for forming dual work function gate electrodes in a semiconductor device
A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly...
US-7,430,141 Method and apparatus for memory data deskewing
A memory interface (20) for receiving memory signals individually synchronizes data signals to a delayed strobe signal in order to reduce the spread of the data...
US-7,430,072 System and method for increasing image quality in a display system
System and method for maximizing image quality by eliminating vias on a reflective surface. A preferred embodiment comprises depositing a first portion of a...
US-7,429,895 Systems and methods for drift compensation in a control circuit
Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes...
US-7,429,524 Transistor design self-aligned to contact
The present invention provides a method of manufacturing a transistor device, a transistor device, and a method for manufacturing an integrated circuit. In one...
US-7,429,517 CMOS transistor using high stress liner layer
A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor...
US-7,428,719 Layout of network using parallel and series elements
Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically...
US-7,428,666 Apparatus and method for trace stream identification of a pipeline flattener secondary code flush following a...
When an INTERRUPT SERVICE ROUTINE (SECONDARY) CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a...
US-7,428,664 Protocol replay system
An expert protocol analyzer, which records a protocol exchange between two or more hardware devices on a network or software modules in a multiprogramming...
US-7,428,282 Timing recovery of PAM signals using baud rate interpolation
A timing recovery method enables interpolation of PAM signals sampled at baud rate. The method exploits the structure of the PAM signal and also the smoothness...
US-7,428,281 System and method of removing discrete spurious signals in cable broadband and other RF environments
A system and method of removing discrete spurious signals in cable broadband environments as well as in other RF environments employs either non-decision...
US-7,427,940 Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, SOC...
A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity...
US-7,427,898 Detecting amplifier out-of-range conditions
Out-of-range conditions are detected in amplifier CMOS or BiCMOS circuitry that includes a control transistor (M.sub.S) connected in series with a cascode...
US-7,427,852 Low power control mode for power supply
Systems and methods are disclosed to mitigate power consumption in a power supply, such as when operating in a low power mode. One aspect of the present...
US-7,427,795 Drain-extended MOS transistors and methods for making the same
Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer...
US-7,427,787 Guardringed SCR ESD protection
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an...
US-7,427,543 Method to improve drive current by increasing the effective area of an electrode
The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100...
US-7,426,683 Semiconductor memory device equipped with error correction circuit
The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that...
US-7,426,419 Scheduling system and method
Photolithography operation in a wafer fab using relative weightings of work in progress to iteratively schedule wafers.
US-7,425,994 Video decoder with different signal types processed by common analog-to-digital converter
A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also...
US-7,425,911 Signal-to-noise ratio when using fewer bits than the number of output bits of an analog to digital converter
Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of...
US-7,425,874 All-digital phase-locked loop for a digital pulse-width modulator
A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a ...
US-7,425,864 Recovery from clipping events in a class D amplifier
A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20),...
US-7,425,859 Apparatus and method for generating pulses
An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for...
US-7,425,848 Integrated driver circuit structure
An integrated circuit driver structure, comprising an amplifier, a current mirror block and an external current set resistor, is provided that is digitally...
US-7,425,512 Method for etching a substrate and a device formed using the method
The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and...
US-7,425,502 Minimizing resist poisoning in the manufacture of semiconductor devices
The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The...
US-7,424,699 Modifying sub-resolution assist features according to rule-based and model-based techniques
Modifying sub-resolution assist features includes receiving a mask pattern for a photolithographic mask. The mask pattern includes main features, and the...
US-7,424,654 Method and apparatus for performing multi-site integrated circuit device testing
Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the...
US-7,423,799 Method for adjusting the resonant frequency of an oscillating device
A method for increasing the resonant frequency of a torsional hinged device having a reduced attaching area between the torsional hinges and the supporting...
US-7,423,729 Method of monitoring the light integrator of a photolithography system
A method of monitoring a light integrator of a photolithography system, wherein the photolithography system comprises a light source for illuminating different...
US-7,423,566 Sigma-delta modulator using a passive filter
A sigma-delta modulator includes a discrete time circuit that receives a digital feedback signal and an input signal, where the input signal includes information...
US-7,423,565 Apparatus and method for comparison of a plurality of analog signals with selected signals
In response to a selected analog applied to the input terminal of an analog-to-digital converter, the digitized output signal is stored in a buffer/register. In...
US-7,423,475 Providing optimal supply voltage to integrated circuits
A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the...
US-7,423,469 Triangulating phase interpolator
There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current...
US-7,423,442 System and method for early qualification of semiconductor devices
According to one embodiment of the invention, a method for early qualification of semiconductor device includes performing initial testing on a semiconductor...
US-7,423,410 Battery protecting circuit
This invention provides a battery protecting circuit where even if the battery voltage falls nearly to zero volts due to overdischarge or the like while an NMOS...
US-7,423,344 Bi-layer etch stop process for defect reduction and via stress migration improvement
A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric...
US-7,423,326 Integrated circuits with composite gate dielectric
CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a...
US-7,422,972 On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and...
An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing...
US-7,422,969 Multi-step process for patterning a metal gate electrode
The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method...
US-7,422,968 Method for manufacturing a semiconductor device having silicided regions
The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the...
US-7,422,967 Method for manufacturing a semiconductor device containing metal silicide regions
The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for...
US-7,422,920 Method and forming a micromirror array device with a small pitch size
A spatial light modulator is disclosed, along with a method for making such a modulator that comprises an array of micromirror devices. The center-to-center...
US-7,421,634 Sequential scan based techniques to test interface between modules designed to operate at different frequencies
According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan...
US-7,421,633 Controller receiving combined TMS/TDI and suppyling separate TMS and TDI
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-7,421,018 System and method for selecting precursor equalizer coefficients and serializer deserializer incorporating the same
In one aspect, the present invention provides a system and method for selecting precursor equalizer coefficients and a serializer deserializer (SERDES)...
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