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Patent # Description
US-9,535,439 LDO current limit control with sense and control transistors
A circuit and method for providing a current limiting feature in a low dropout ("LDO") linear voltage regulator. A pass element generates an output voltage that...
US-9,535,127 Tester, parallel scan paths, and comparators in same functional circuits
An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the...
US-9,535,126 Tap, test, CSU, scan circuitry with top and bottom contacts
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,535,125 Tap decay test circuitry having capture test strobe enable input
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-9,535,124 TAP gated updateDR output AUX test control of WSP update
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture,...
US-9,535,123 Frequency scaled segmented scan chain for integrated circuits
A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a...
US-9,535,122 Serial/parallel control, separate tap, master reset synchronizer for tap domains
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG...
US-9,535,118 TAP addressable circuit with bi-directional TMS and second signal lead
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-9,533,618 Method, apparatus and system for processing a display from a surround view camera solution
A method, apparatus and a system multi-camera image processing method. The method includes performing geometric alignment to produce a geometric output,...
US-9,532,230 Method and apparatus for transmitting LTE waveforms in shared spectrum by carrier sensing
A method of operating a long term evolution (LTE) communication system on a shared frequency spectrum is disclosed. A user equipment (UE) is initialized on an...
US-9,531,563 Efficient fairness allocation in powerline CSMA/CA protocols
Transmission over a communication channel using carrier sense multiple access collision avoidance (CSMA/CA) may be performed by determining for each frame if...
US-9,531,372 Driver with transformer feedback
A driver circuit includes an input drive stage, an output drive stage, and a transformer. The input drive stage is configured to receive a differential input...
US-9,531,343 Systems and methods of variable fractional rate digital resampling
Example embodiments of the systems and methods of variable fractional rate digital resampling as disclosed herein achieve variable rate conversion. In the...
US-9,531,335 Method and circuitry for CMOS transconductor linearization
Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the...
US-9,531,267 DC-DC converter using internal ripple with the DCM function
A DC-DC converter, having an input voltage and an output voltage, includes an inductor and a switch switching the input voltage to an input side of the...
US-9,529,411 Power-saving mode for USB power delivery sourcing device
Methods of reducing power consumption in a USB power-delivery source device. In one such method, one or more source capabilities messages are sent by the USB...
US-9,529,375 Single inductor-multiple output DC-DC converter, method for operating the same and electronic device comprising...
Single inductor-multiple output (SIMO) DC-DC converter, having an output node which is coupled to one side of the single inductor to receive a load current. A...
US-9,529,334 Rotational transition based clock, rotational spectroscopy cell, and method of making same
Described examples include a millimeter wave atomic clock apparatus, chip scale vapor cell, and fabrication method in which a low pressure dipolar molecule gas...
US-9,529,045 Taps with class T0-T2, T4 capabilities and topology selection logic
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
US-9,529,043 Tap counting circuit scan clock prime and enable prime leads
The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with...
US-9,527,728 Integrated circuit package and method
A method of forming a packaged electronic device includes fabricating a MEMS structure, such as a BAW structure, on a first semiconductor wafer substrate;...
US-9,525,977 Broadcast multicast mode
A broadcast/multicast transmission format includes a data portion and a cyclic prefix (CP) coupled to the traffic data portion. A method and system for...
US-9,525,865 Fault detection and method of detecting faults in digital imaging systems
A method of analyzing a digital camera includes generating first image data using an image sensor in the camera. A first analysis is performed on at least one...
US-9,525,350 Cascaded buck boost DC to DC converter and controller for smooth transition between buck mode and boost mode
Cascaded buck boost DC to DC conversion systems, controllers and methods are presented, in which a buck converter stage is pulse width modulated in a first mode...
US-9,525,077 Integration of a baritt diode
A vertically oriented BARITT diode is formed in an integrated circuit. The BARITT diode has a source proximate to the top surface of the substrate of the...
US-9,525,060 Reduced area power devices using deep trench isolation
An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with...
US-9,525,035 Vertical high-voltage MOS transistor and method of forming the same
A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method...
US-9,525,021 Methods and apparatus for high voltage integrated circuit capacitors
High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate...
US-9,524,926 Packaged device with additive substrate surface modification
A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a...
US-9,524,881 Method for fabricating specific termination angles in titanium tungsten layers
Method of forming a termination angle in a titanium tungsten layer include providing a titanium tungsten layer and applying a photo resist material to the...
US-9,524,069 Keypad with 1-bit capacitive touch sensing analog front end with sparse multi-touch detection
A capacitive touch keypad may receive a touch by a conductive object to one or more keys of the keypad, in which the keys each have a separate capacitive key...
US-9,524,059 Interaction detection using structured light images
An apparatus and method are provided to determine the occurrence and location of an interaction with an interface, particularly with an image of a user...
US-9,523,756 Systems and methods of input power and current measurement
As disclosed herein, a PFC control device, may be used for power factor correction and for input power and current measurement simultaneously. To determine the...
US-9,523,738 TCK/TMS(C) counter circuitry with third, fourth count and reset outputs
Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path....
US-9,523,733 Automatic test equipment for testing an oscillating crystal and method for operating the same
Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic...
US-9,523,724 Tracking energy consumption using a boost technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,521,662 Uplink synchronization management in wireless networks
In at least some embodiments, a wireless networking system is provided. The wireless networking system includes a base-station and a plurality of user devices...
US-9,521,614 Power efficient method for Wi-Fi home automation
A method for automation and control of a wireless device in a WiFi environment. The method includes a wireless mobile device configured with a soft access point...
US-9,520,989 Phase detector and retimer for clock and data recovery circuits
A phase detector and retimer circuit that includes a retimer circuit, a phase shift circuit coupled to the retimer circuit, and an error signal generation...
US-9,520,884 Phase lock loop with dynamic lock ranges
A phase look loop (PLL) device has a dynamic lock range that is based on a temperature measured during a calibration process. The PLL device includes a...
US-9,520,881 Systems and methods for tuning an oscillator frequency
A system for tuning an oscillator frequency. The system includes a trimmed calibration circuit comprising a comparator and trimmed delay element and calibration...
US-9,520,880 Configurable analog front ends for circuits with substantially gate enclosed inner electrode MOSFET switch
A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a...
US-9,520,879 Adaptive blanking timer for short circuit detection
A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS...
US-9,520,863 Dual-port negative level sensitive preset data retention latch
In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is...
US-9,520,862 Dual-port negative level sensitive reset preset data retention latch
In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch....
US-9,520,861 System and method for harmonic suppression
A system to generate an oscillator signal. The system includes a multi-stage oscillator, where each stage generates an output. The system also includes a first...
US-9,520,849 Rail-to-rail constant transconductance differential input stage
A primary differential input pair of transistors and a secondary differential input pair of transistors are capable of operating in parallel to provide load...
US-9,520,822 Circuits and methods for driving eccentric rotating mass motors
Circuits and methods for driving ERM motors are disclosed herein. An embodiment of the circuit includes an input, wherein an input signal is receivable at the...
US-9,520,811 Capacitive micromachined ultrasonic transducer (CMUT) device with through-substrate via (TSV)
A Capacitive Micromachined Ultrasonic Transducer (CMUT) device includes at least one CMUT cell including a first substrate having a top side including a...
US-9,520,461 Integrated circuit with lateral flux capacitor
An integrated circuit has a lateral flux capacitor assembly that includes a first metal layer having a capacitive portion with first and second lateral sides...
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