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Patent # Description
US-7,403,774 Unconnected power save mode for improving battery life of wireless stations in wireless local area networks
An unconnected power save method reduces the battery consumption of a wireless station in a wireless local area network (WLAN). A wireless station enters a sleep...
US-7,403,719 Feedback control for free-space optical systems
Disclosed is a system and method for aligning a free-space optical signal in an optical system having a light modulator having an array of pixels. In this system...
US-7,403,604 Method and apparatus for activating extended services in a user device using a voice over packet gateway
An enhanced services display message protocol (ESDMP) facilitates display of messages in a compliant analog telephony device (ATD). An exemplary gateway device...
US-7,403,569 Efficient low-power mode for multicarrier communications
Multicarrier modulated communications, involving a transmitting modem (30; 30') and a receiving modem (40; 40') that operate according to normal operating mode...
US-7,403,531 WLAN admission control for multimedia service
The present invention provides a system for controlling isochronous data admission, within a WLAN system (102) that transports both isochronous and asynchronous...
US-7,403,511 Low power packet detector for low power WLAN devices
A low power packet detector (LPPD) can significantly reduce the average power consumption of WLAN devices. The LPPD takes advantages of 802.11 protocols to turn...
US-7,403,507 System and method for recovering system time in direct sequence spread spectrum communications
A sleep control system and method are provided that permit a reference clock and the direct sequence spread spectrum (DSSS) modem in a mobile station receiver to...
US-7,403,324 Double substrate reflective spatial light modulator with self-limiting micro-mechanical elements
A spatial light modulator has an array of reflective surfaces of deflectable mirror plates. For improving the reflectivity of the mirror plates, layers that are...
US-7,403,213 Boundary dispersion for artifact mitigation
A method and system providing boundary dispersion to pixel values displayed on a binary spatial light modulator to reduce temporal contouring artifacts. Pixel...
US-7,403,187 Generalized reset conflict resolution of load/reset sequences for spatial light modulators
Disclosed herein are methods for providing a load/reset sequence for a visual display system (100) having a phased reset spatial light modulator (SLM) (14). The...
US-7,403,095 Thin film resistor structure and method of fabricating a thin film resistor structure
A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical...
US-7,403,094 Thin film resistor and dummy fill structure and method to improve stability and reduce self-heating
An integrated circuit thin film resistor structure includes a first dielectric layer (18A) disposed on a semiconductor layer (16), a first dummy fill layer (9A)...
US-7,402,893 System and method for improved auto-boating
According to one embodiment of the invention, a system used in auto-boating includes a tape substrate supported by a boat. The tape substrate includes a pair of...
US-7,402,880 Isolation layer for semiconductor devices and method for forming the same
According to one embodiment of the present invention, a semiconductor device includes a first layer of dielectric material disposed upon an upper surface of a...
US-7,402,878 Packaging method for microstructure and semiconductor devices
A novel method of packaging electronic devices (e.g. any device that receives or transmits electronic signals) including microelectromechanical devices,...
US-7,402,874 One time programmable EPROM fabrication in STI CMOS technology
The formation of a one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell (100)...
US-7,402,535 Method of incorporating stress into a transistor channel by use of a backside layer
The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located...
US-7,402,524 Post high voltage gate oxide pattern high-vacuum outgas surface treatment
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage...
US-7,402,514 Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and...
An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is...
US-7,402,458 Stress relieved flat frame for DMD window
An improved window frame and window piece for a micromirror assembly is disclosed herein. The window frame includes a stress-relieving contour positioned in the...
US-7,402,270 Method and system for integrated circuit packaging
According to one embodiment of the invention, a mold tool for packaging integrated circuits includes a first mold press die including a first non-planar surface...
US-7,401,875 Inkjet printhead incorporating a memory array
A thermal inkjet printhead 100 of the present invention includes a heating element 110, an ink chamber, control circuitry 108, an ink reservoir, and a memory...
US-7,400,903 Wireless communications system using both licensed and unlicensed frequency bands
A communications system including devices (10, 20) for transmitting and receiving wireless communications over licensed and unlicensed bands is disclosed. On the...
US-7,400,870 Hardware loop for automatic gain control
A hardware control loop (19) derives an AGC setting for a communication receiver based on signal strength information (16), without incurring program execution...
US-7,400,608 Method and apparatus for spread spectrum interference cancellation
The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator,...
US-7,400,523 8T SRAM cell with higher voltage on the read WL
The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry...
US-7,400,130 Integrated circuit device
An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a...
US-7,400,128 Current-mode bandgap reference voltage variation compensation
A circuit and method for reducing the variation of a reference voltage as a function of resistivity .rho. in a current-mode bandgap reference circuit generating...
US-7,400,121 Soft-start system for voltage regulator and method of implementing soft-start
A system and method to provide a slow start up voltage, such as that can slowly ramp up or down by cyclically coupling a pair of associated energy storage...
US-7,400,064 DC/DC power converter
A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The...
US-7,400,025 Integrated circuit inductor with integrated vias
Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous...
US-7,398,493 Isolated pwell tank verification using node breakers
A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from...
US-7,397,870 Ultra-wideband (UWB) receiver
System and method for maximizing a signal strength of a received signal pulse. A preferred embodiment comprises a self-adjusting correlator/integrator (for...
US-7,397,779 Minimizing handoffs and handoff times in wireless local area networks
A method for reducing the number of channels that are scanned during a handoff situation for a wireless endpoint station in a wireless local area network (WLAN),...
US-7,397,410 Input tracking high-level multibit quantizer for delta-sigma ADC
A quantization circuit includes a plurality of resistors, a plurality of tap points, and a plurality of coarse comparators. Each coarse comparator has a first...
US-7,397,107 Ferromagnetic capacitor
An integrated circuit capacitor having a bottom plate 50a, a dielectric layer 250', and a ferromagnetic top plate 20a.
US-7,397,085 Thermal coupling of matched SOI device bodies
Performance matching devices in SOI are improved by thermally isolating matched devices within a continuous body of active material. Matched devices are isolated...
US-7,397,046 Method for implanter angle verification and calibration
Methods (300, 400) are described for calibrating the implantation angle of an ion implanter utilized in the manufacture of semiconductor products. One method...
US-7,396,755 Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer
The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140...
US-7,396,728 Methods of improving drive currents by employing strain inducing STI liners
A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard...
US-7,396,722 Memory device with reduced cell area
The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active...
US-7,396,716 Method to obtain fully silicided poly gate
The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate...
US-7,395,471 Connection of auxiliary circuitry to tap and instruction register controls
The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG...
US-7,395,467 Remove signal from TAP selection circuitry to multiplexer control circuitry
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is...
US-7,395,413 System to dispatch several instructions on available hardware resources
A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions...
US-7,395,307 Carry look-ahead circuit and adder using same
A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102,...
US-7,394,877 Low-power packet detection using decimated correlation
A method and apparatus is presented for detecting the presence of a packet being transmitted on a communications medium using self-correlation of samples taken...
US-7,394,876 Enhanced channel estimator, method of enhanced channel estimating and an OFDM receiver employing the same
The present invention provides an enhanced channel estimator for use with an orthogonal frequency division multiplex (OFDM) receiver employing scattered pilot...
US-7,394,875 Beaulieu series approach to optimal UMTS RACH preamble detection estimation
A method for preamble detection in mobile unit to base unit wireless telephony sets a preamble detection threshold based upon a Beaulieu series computation...
US-7,394,867 Code division multiple access wireless system with closed loop mode using ninety degree phase rotation and...
A wireless communication system (10). The system comprises a user station (12). The user station comprises despreading circuitry (22) for receiving and...
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