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Delay-locked loop circuit
The delay of delay circuit 10 is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal .phi.in when transition is...
MEMS fabrication method
A method for singulating a substrate such as a semiconductor wafer populated with a plurality of MEMS devices. A preferred embodiment of the present invention...
Wafer matching methods for use in assembling micromirror array devices
The invention provides a method for matching micromirror wafers and electrode wafers so as to form micromirror array devices while the production yield is...
CAM test structures and methods therefor
Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes....
Register move instruction for section select of source operand
A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The...
System and method for digital radio receiver
A communications system comprising a processor, a variable oscillator, a radio frequency (RF) quadrature demodulator, a variable capacitor, a continuous-time,...
High speed early/late discrimination systems and methods for clock and
data recovery receivers
The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation...
Rake receiver architecture for an ultra-wideband (UWB) receiver
System and method for combining maximizing a received signal in a multipath environment. A preferred embodiment comprises a rake receiver (for example, rake...
Fast access memory architecture
A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to...
Highly efficient isolated AC/DC power conversion technique
An AC-to-DC power converter that is capable of generating a regulated, isolated DC voltage output from a power factor corrected AC voltage input with improved...
Disk drive fly height control based on constant power dissipation in
read/write head heaters
A fly height controller circuit for a disk drive head having a resistive heater is disclosed. The fly height controller includes an error amplifier that controls...
Method of repairing micromirrors in spatial light modulators
Disclosed herein is method of operating a device that comprises an array of micromirrors. The method comprises a process usable for repairing stuck micromirrors...
Content-dependent scan rate converter with adaptive noise reduction
A content-dependent scan rate converter with adaptive noise reduction that provides a highly integrated, implementation efficient de-interlacer. By identifying...
Systems and methods for providing anti-aliasing in a sample-and-hold
Systems and methods are included for providing anti-aliasing in a sample-and-hold circuit. One embodiment of the present invention includes a method for sampling...
Analog circuit and method for multiplying clock frequency
A signal generating circuit includes a relaxation oscillator operating to alternately generate a first ramp signal that is periodic at a frequency of the...
System and method for increasing radio frequency (RF)/microwave
inductor-capacitor (LC) oscillator frequency...
System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. A preferred embodiment comprises a voltage controlled oscillator...
Low voltage structure for gain boosting in high gain amplifiers
Reducing the bias voltage level required in a boost amplifier enhancing a gain of amplifier comprising first and second amplification stages. In an embodiment,...
Circuit and method for switching active loads of operational amplifier
An operational amplifier having a wide input common mode voltage range includes first (2) and second (3) differential input transistor pairs coupled to first...
Digital storage element architecture comprising dual scan clocks and
A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and...
A charging circuit has a battery 12, switching element 14, and resistor 16 for current detection arranged on the primary side of transformer 10. Diode 18 and...
System and method for exposure of partial edge die
According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer....
System and method for securing the initialization of an inherently
non-secure Smartcard controller
A system and method for securing the initialization of a Smartcard controller and a Smartcard terminal incorporating the system or the method. In one embodiment,...
Achieving desired synchronization at sequential elements while testing
integrated circuits using sequential...
A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated...
Multi-channel DMA with shared FIFO
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with "m" threads...
RSSE optimization using hardware acceleration
A Reduced State Sequence Equalizer (RSSE) is implemented using a butterfly hardware accelerator (58) in the form of a butterfly to increase the efficiency of...
Methods and systems for detecting and mitigating interference for a
In at least some embodiments, a method for mitigating interference between an Ultra Wideband (UWB) device and a non-UWB device is provided. The method includes,...
Incremental redundancy using two stage rate matching for automatic repeat
request to obtain high speed transmission
Methods and apparatus for processing a data stream for high speed wireless Transmission. At the transmission side, the methods and apparatus rate-match an...
Wireless communications system with cycling of unique cell bit sequences
in station communications
A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver...
Match sensing circuit for a content addressable memory device
A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match...
Apparatus and method for applying write signals for driving a write head
An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first...
Real-time content based gamma adjustment for digital video display
Methods for improving video images by making real-time gamma correction adjustments to such images are described. More particularly, gamma correction adjustments...
Digital-to-analog converter with triode region transistors in
System and method for high-speed and high-precision digital to analog conversion. A preferred embodiment comprises a dual-resistor ladder digital-to-analog...
Programmable serializer for a video display
A serializer receives parallel data and a control signal. The serializer splits the parallel data into multiple subportions of data and, based on the control...
Precision frequency and phase synthesis with fewer voltage-controlled
A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a...
Efficient current monitoring for DC-DC converters
A current monitoring circuit for DC-DC switching converters includes a track and latch comparator circuit (30) having a preamplifier (32) that is controlled...
Output load adaptable MOSFET gate drive voltage level in a DC-DC
The output current of a fixed-frequency DC to DC converter is sensed, creating a voltage representative of the load current. This voltage is then compared to one...
Sub-lithographics opening for back contact or back gate
A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in...
Silicon recess improvement through improved post implant resist removal
The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a...
Method and apparatus for attaching an IC package to a PCB assembly
A technique for attaching solder balls of a BGA to a PCB. In one example embodiment, this is accomplished by applying solder paste onto at least one of a...
Trench isolation structure and a method of manufacture therefor
The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the...
Method for manufacturing a transistor device having an improved breakdown
voltage and a method for...
The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The...
Data signal demodulation in a communication system
A method described evaluates the pilot-to-data power ratio based on the values of the demodulated data at the output of a receiver such as a conventional maximal...
Power protection for VCM control loop in hard disk drive servo IC
A VCM power protection circuit that limits the maximum voltage that can occur across any of the VCM's output FETs, while at the same time providing some bias on...
Method of recovering digital data from a clocked serial input signal and
clocked data recovery circuit
Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to...
System and method for clamping a differential amplifier
System and method for limiting an output signal of a differential amplifier. A preferred embodiment comprises a limit sense amplifier configured to detect when...
Low cost method to produce high volume lead frames
A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222)...
Integrated circuit having a doped porous dielectric and method of
manufacturing the same
In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a...
Method for selective deposition of a thin self-assembled monolayer
A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is...
Semiconductor device having post-mold nickel/palladium/gold plated leads
A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of...
Fabricating die with separate test pads selectively coupled to cores
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test...