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Patent # Description
US-7,387,956 Refractory metal-based electrodes for work function setting in semiconductor devices
The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate...
US-7,387,916 Sharp corner lead frame
An integrated circuit package lead frame, comprising a plurality of leads and a spine electrically connected to said plurality of leads, said spine comprising...
US-7,386,671 Smart cache
A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be...
US-7,386,447 Speech coder and method
An overflow problem of LSF quantization in G.729 Annex B speech encoding which may lead to non-assignment of a codebook index. Preferred embodiments fix the...
US-7,386,444 Hybrid speech coding and system
Hybrid linear predictive speech coding system with phase alignment predictive quantization zero phase alignment of speech prior to waveform coding aligns...
US-7,386,326 Programmable task-based co-processor
A programmable co-processor system comprising a datapath, a microprogram, and a microcontroller is provided. The datapath includes one or more datapath elements...
US-7,386,182 Optimization of multiple feature lithography
According to one embodiment of the invention, a method for enhancing multiple feature lithography is provided. The method includes generating a plurality of maps...
US-7,386,170 Image object ranking
Automatic vision system object indexing and image database query system using both path-dependent and path-independent features of moving objects within a...
US-7,386,076 Space time encoded wireless communication system with multipath resolution receivers
A wireless receiver (30.sub.1) for receiving multiple space time encoded signals from a plurality of transmit antenna sets (TAT.sub.1 through TAT.sub.2, and...
US-7,386,075 Apparatus for and method of optimizing the performance of a radio frequency receiver in the presence of...
An apparatus for and method of extending the dynamic range of a RF communications receiver. The invention provides a mechanism for controlling the gain of both...
US-7,386,030 Automatic threshold selection method for improving the detection of a wireless signal
System and method for improving the detection performance of a wirelessly transmitted signal. A preferred embodiment comprises specifying a desired response for...
US-7,385,864 SRAM static noise margin test structure suitable for on chip parametric measurements
A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement...
US-7,385,841 Static random access memory device having a voltage-controlled word line driver for retain till accessed mode...
A static random-access memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) a row of SRAM cells coupled to a...
US-7,385,840 SRAM cell with independent static noise margin, trip voltage, and read current optimization
An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell...
US-7,385,747 Illumination system with integral modulation technique
A system and method for the modulation of light propagating along an optical path, for example the optical path in a projection display system. As light in the...
US-7,385,539 All-digital phase locked loop (ADPLL) system
An all-digital phase locked loop system for generating an oscillator output signal under control of a digital reference input. The system comprises a digitally...
US-7,385,537 Linear feedback shift register first-order noise generator
A first-order signal generator (135). The generator comprises a shift register (210') having a number N of bit positions. Each bit position is operable to store...
US-7,385,536 Methods and circuits for output of sample-and-hold in pipelined ADC
Methods and circuit embodiments are disclosed for implementing an improved signal path for a sample-and-hold output. In exemplary embodiments, a sample-and-hold...
US-7,385,440 Bootstrapped switch for sampling inputs with a signal range greater than supply voltage
A bootstrapped circuit for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an...
US-7,385,383 Methods and systems for determining efficacy of stress protection circuitry
Methods and systems are provided for determining efficacy of stress protection circuitry. The methods and systems employ a ring oscillator that models at least...
US-7,385,202 Divergent charged particle implantation for improved transistor symmetry
The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for...
US-7,384,869 Protection of silicon from phosphoric acid using thick chemical oxide
A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments...
US-7,384,861 Strain modulation employing process techniques for CMOS technologies
A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the...
US-7,384,855 Resistor integration structure and technique for noise elimination
A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate...
US-7,384,839 SRAM cell with asymmetrical transistors for reduced leakage
A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The...
US-7,383,367 Progressive extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least...
US-7,383,343 System using portal service interface to request and determine QOS requirements on non-QOS capable device on a...
An engineering model is described for a home gateway and interface system and method for providing quality of service to a home LAN device on a home network that...
US-7,382,832 Scalable time-switched preamble supplement generator, method of generating and multiple-input, multiple-output...
The present invention provides a time-switched preamble supplement generator for use with a multiple-input, multiple-output (MIMO) transmitter employing N...
US-7,382,719 Scalable and backwards compatible preamble for OFDM systems
A method comprising encoding a plurality of signals according to a predetermined negation scheme and transmitting the plurality of signals, wherein each signal...
US-7,382,560 Low power servo mode write driver
A circuit (40) for use in a mass data storage device (10) has first (44) second (46) current driver circuits for providing write currents to the data transducer...
US-7,382,200 Type-II all-digital phase-locked loop (PLL)
System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop...
US-7,382,147 Semiconductor device testing
An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines...
US-7,381,950 Characterizing dimensions of structures via scanning probe microscopy
A method comprising characterizing the dimensions of structures on a semiconductor device having dimensions less than approximately 100 nanometers (nm) using one...
US-7,380,947 Multi-step turn off mode for projection display
Disclosed herein is a method of operating display systems with reduction of the warm-up time of an arc lamp in the event of an accidental or unintentional turn-off.
US-7,380,200 Soft error detection and correction by 2-dimensional parity
The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial....
US-7,380,185 Reduced pin count scan chain implementation
The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data...
US-7,380,184 Sequential scan technique providing enhanced fault coverage in an integrated circuit
According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the...
US-7,380,153 Micropipeline stage controller and control scheme
A technique for controlling local events in two-phase asynchronous handshake circuits.
US-7,380,150 Method for selecting an inductive or battery power supply based on the voltage sensed therefrom for a...
A power management circuit for a system that has combined power supplies from an inductively coupled circuit and from a battery comprises voltage sensing...
US-7,380,070 Organization of dirty bits for a write-back cache
A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit...
US-7,380,040 Software programmable dynamic arbitration scheme
A method for arbitration among a plurality of requesting devices for a shared resource in which one device is an ultra high priority device grants access to one...
US-7,379,619 System and method for two-dimensional keystone correction for aerial imaging
A digital keystone correction process locates image points in a corrected image from image points in a distorted image that was produced by misalignment of the...
US-7,379,514 Phase advance compensation for MIMO time-switch preamble modes
A communications receiver is provided that includes a first and second compensators a pilot tracker and a demodulator. The first compensator is operable to...
US-7,379,462 WLAN access scheduling control
A system for scheduling access times for transmitting data traffic in a WLAN including both isochronous streams and asynchronous bursts characterized by widely...
US-7,379,374 Virtual ground circuit for reducing SRAM standby power
A method of operating a memory circuit having a plurality of blocks of memory cells (400-404) is disclosed. The method includes storing data in the plurality of...
US-7,379,354 Methods and apparatus to provide voltage control for SRAM write assist circuits
Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write...
US-7,378,951 Tire pressure monitoring system
A vehicular tire pressure monitoring system, including a transponder unit (10) for each tire to be monitored, the transponder unit having an incorporated RF...
US-7,378,904 Soft transitions between muted and unmuted states in class D audio amplifiers
A class AD audio amplifier system (10) with reduced noise capability in muting and unmuting events is disclosed. The amplifier system (10) includes multiple...
US-7,378,888 Delay-locked loop circuit
The delay of delay circuit 10 is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal .phi.in when transition is...
US-7,378,293 MEMS fabrication method
A method for singulating a substrate such as a semiconductor wafer populated with a plurality of MEMS devices. A preferred embodiment of the present invention...
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