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Patent # Description
US-7,375,567 Digital storage element architecture comprising dual scan clocks and preset functionality
A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and...
US-7,375,471 Charging circuit
A charging circuit has a battery 12, switching element 14, and resistor 16 for current detection arranged on the primary side of transformer 10. Diode 18 and...
US-7,374,866 System and method for exposure of partial edge die
According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer....
US-7,374,080 System and method for securing the initialization of an inherently non-secure Smartcard controller
A system and method for securing the initialization of a Smartcard controller and a Smartcard terminal incorporating the system or the method. In one embodiment,...
US-7,373,571 Achieving desired synchronization at sequential elements while testing integrated circuits using sequential...
A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated...
US-7,373,437 Multi-channel DMA with shared FIFO
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with "m" threads...
US-7,372,922 RSSE optimization using hardware acceleration
A Reduced State Sequence Equalizer (RSSE) is implemented using a butterfly hardware accelerator (58) in the form of a butterfly to increase the efficiency of...
US-7,372,890 Methods and systems for detecting and mitigating interference for a wireless device
In at least some embodiments, a method for mitigating interference between an Ultra Wideband (UWB) device and a non-UWB device is provided. The method includes,...
US-7,372,837 Incremental redundancy using two stage rate matching for automatic repeat request to obtain high speed transmission
Methods and apparatus for processing a data stream for high speed wireless Transmission. At the transmission side, the methods and apparatus rate-match an...
US-7,372,825 Wireless communications system with cycling of unique cell bit sequences in station communications
A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver...
US-7,372,713 Match sensing circuit for a content addressable memory device
A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match...
US-7,372,649 Apparatus and method for applying write signals for driving a write head
An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first...
US-7,372,507 Real-time content based gamma adjustment for digital video display
Methods for improving video images by making real-time gamma correction adjustments to such images are described. More particularly, gamma correction adjustments...
US-7,372,387 Digital-to-analog converter with triode region transistors in resistor/switch network
System and method for high-speed and high-precision digital to analog conversion. A preferred embodiment comprises a dual-resistor ladder digital-to-analog...
US-7,372,381 Programmable serializer for a video display
A serializer receives parallel data and a control signal. The serializer splits the parallel data into multiple subportions of data and, based on the control...
US-7,372,340 Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages
A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a...
US-7,372,307 Efficient current monitoring for DC-DC converters
A current monitoring circuit for DC-DC switching converters includes a track and latch comparator circuit (30) having a preamplifier (32) that is controlled...
US-7,372,240 Output load adaptable MOSFET gate drive voltage level in a DC-DC controller
The output current of a fixed-frequency DC to DC converter is sensed, creating a voltage representative of the load current. This voltage is then compared to one...
US-7,372,101 Sub-lithographics opening for back contact or back gate
A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in...
US-7,371,691 Silicon recess improvement through improved post implant resist removal and cleans
The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a...
US-7,371,673 Method and apparatus for attaching an IC package to a PCB assembly
A technique for attaching solder balls of a BGA to a PCB. In one example embodiment, this is accomplished by applying solder paste onto at least one of a...
US-7,371,658 Trench isolation structure and a method of manufacture therefor
The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the...
US-7,371,648 Method for manufacturing a transistor device having an improved breakdown voltage and a method for...
The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The...
US-7,369,523 Data signal demodulation in a communication system
A method described evaluates the pilot-to-data power ratio based on the values of the demodulated data at the output of a receiver such as a conventional maximal...
US-7,369,350 Power protection for VCM control loop in hard disk drive servo IC
A VCM power protection circuit that limits the maximum voltage that can occur across any of the VCM's output FETs, while at the same time providing some bias on...
US-7,369,068 Method of recovering digital data from a clocked serial input signal and clocked data recovery circuit
Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to...
US-7,368,991 System and method for clamping a differential amplifier
System and method for limiting an output signal of a differential amplifier. A preferred embodiment comprises a limit sense amplifier configured to detect when...
US-7,368,807 Low cost method to produce high volume lead frames
A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222)...
US-7,368,401 Integrated circuit having a doped porous dielectric and method of manufacturing the same
In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a...
US-7,368,377 Method for selective deposition of a thin self-assembled monolayer
A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is...
US-7,368,328 Semiconductor device having post-mold nickel/palladium/gold plated leads
A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of...
US-7,368,304 Fabricating die with separate test pads selectively coupled to cores
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test...
US-7,366,809 Pipelined stop, start, address byte, and data byte technique and circuit for I.sup.2C logic system
Data speed in an I.sup.2C system is increased by operating a master CPU (110) to pipeline a stop/start/address byte transfer instruction by setting a stop bit,...
US-7,366,658 Noise pre-processor for enhanced variable rate speech codec
An enhanced noise pre-processor in a speech codec smoothes channel energy estimate moving toward a first smoothing constant if a prior signal to noise ratio...
US-7,366,649 Method for generating and evaluating a table model for circuit simulation
A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table...
US-7,366,623 Method and apparatus for characterizing a load on a data line
A method for characterizing a load on a data line includes the steps of: (A) Applying at least three successive voltages to the data line. Each respective...
US-7,366,266 Space time block coded transmit antenna diversity for WCDMA
A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (r.sub.j(i+.tau..sub.j), i=0-N-1) during a first...
US-7,366,201 Method and apparatus for vector based sequence generation
A vector-based sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of...
US-7,365,898 Sloping electrodes in a spatial light modulator
A method of tilting a micromirror includes forming a substrate, a micromirror outwardly from the substrate, and at least one electrode inwardly from the...
US-7,365,609 Hybrid stochastic gradient based digitally controlled oscillator gain K.sub.DCO estimation
A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The...
US-7,365,586 Hysteresis-type input circuit
Hysteresis circuit 10 is composed of three inverters 40, 42, 44. Node N.sub.B in hysteresis circuit 10 is connected to the input terminal of transition-detecting...
US-7,365,556 Semiconductor device testing
An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines...
US-7,364,326 Multiple light source illumination for image display systems
A method for transmitting light in an image display system includes generating a first cone of light from a first light source. The first cone of light includes...
US-7,363,604 Accurate noise modeling in digital designs
A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions...
US-7,363,568 System and method for testing differential signal crossover using undersampling
System and method for testing differential signal crossover in high-speed electronic equipment. A preferred embodiment comprises a test circuit coupled to a...
US-7,363,409 Interrupt control system and method for reducing interrupt latency
An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a...
US-7,363,219 Hybrid speech coding and system
Hybrid linear predictive speech coding system with phase alignment predictive quantization zero phase alignment of speech prior to waveform coding aligns...
US-7,362,530 Amplifier apparatus for use with a sensor
An amplifier apparatus for use with a sensor includes: (a) a first and a second amplifying circuit segment coupled with the sensor and cooperating to effect...
US-7,362,495 Electrostatic fins for a MEMS device
A MEMS device includes a hinge that is disposed outwardly from a substrate and capable of at least partially supporting a conductor that is disposed outwardly...
US-7,362,494 Micromirror devices and methods of making the same
A method for making a micromirror device comprises is disclosed herein.
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