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Patent # Description
US-7,380,200 Soft error detection and correction by 2-dimensional parity
The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial....
US-7,380,185 Reduced pin count scan chain implementation
The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data...
US-7,380,184 Sequential scan technique providing enhanced fault coverage in an integrated circuit
According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the...
US-7,380,153 Micropipeline stage controller and control scheme
A technique for controlling local events in two-phase asynchronous handshake circuits.
US-7,380,150 Method for selecting an inductive or battery power supply based on the voltage sensed therefrom for a...
A power management circuit for a system that has combined power supplies from an inductively coupled circuit and from a battery comprises voltage sensing...
US-7,380,070 Organization of dirty bits for a write-back cache
A cache system is constructed in accordance with an architecture that comprises a tag array into which tags are stored that are used to determine whether a hit...
US-7,380,040 Software programmable dynamic arbitration scheme
A method for arbitration among a plurality of requesting devices for a shared resource in which one device is an ultra high priority device grants access to one...
US-7,379,619 System and method for two-dimensional keystone correction for aerial imaging
A digital keystone correction process locates image points in a corrected image from image points in a distorted image that was produced by misalignment of the...
US-7,379,514 Phase advance compensation for MIMO time-switch preamble modes
A communications receiver is provided that includes a first and second compensators a pilot tracker and a demodulator. The first compensator is operable to...
US-7,379,462 WLAN access scheduling control
A system for scheduling access times for transmitting data traffic in a WLAN including both isochronous streams and asynchronous bursts characterized by widely...
US-7,379,374 Virtual ground circuit for reducing SRAM standby power
A method of operating a memory circuit having a plurality of blocks of memory cells (400-404) is disclosed. The method includes storing data in the plurality of...
US-7,379,354 Methods and apparatus to provide voltage control for SRAM write assist circuits
Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write...
US-7,378,951 Tire pressure monitoring system
A vehicular tire pressure monitoring system, including a transponder unit (10) for each tire to be monitored, the transponder unit having an incorporated RF...
US-7,378,904 Soft transitions between muted and unmuted states in class D audio amplifiers
A class AD audio amplifier system (10) with reduced noise capability in muting and unmuting events is disclosed. The amplifier system (10) includes multiple...
US-7,378,888 Delay-locked loop circuit
The delay of delay circuit 10 is set within a predetermined range, and, in a stop mode, the clock pulses of 1 cycle of clock signal .phi.in when transition is...
US-7,378,293 MEMS fabrication method
A method for singulating a substrate such as a semiconductor wafer populated with a plurality of MEMS devices. A preferred embodiment of the present invention...
US-7,378,287 Wafer matching methods for use in assembling micromirror array devices
The invention provides a method for matching micromirror wafers and electrode wafers so as to form micromirror array devices while the production yield is...
US-7,376,871 CAM test structures and methods therefor
Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes....
US-7,376,813 Register move instruction for section select of source operand
A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The...
US-7,376,400 System and method for digital radio receiver
A communications system comprising a processor, a variable oscillator, a radio frequency (RF) quadrature demodulator, a variable capacitor, a continuous-time,...
US-7,376,211 High speed early/late discrimination systems and methods for clock and data recovery receivers
The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation...
US-7,376,174 Rake receiver architecture for an ultra-wideband (UWB) receiver
System and method for combining maximizing a received signal in a multipath environment. A preferred embodiment comprises a rake receiver (for example, rake...
US-7,376,038 Fast access memory architecture
A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to...
US-7,375,994 Highly efficient isolated AC/DC power conversion technique
An AC-to-DC power converter that is capable of generating a regulated, isolated DC voltage output from a power factor corrected AC voltage input with improved...
US-7,375,912 Disk drive fly height control based on constant power dissipation in read/write head heaters
A fly height controller circuit for a disk drive head having a resistive heater is disclosed. The fly height controller includes an error amplifier that controls...
US-7,375,873 Method of repairing micromirrors in spatial light modulators
Disclosed herein is method of operating a device that comprises an array of micromirrors. The method comprises a process usable for repairing stuck micromirrors...
US-7,375,760 Content-dependent scan rate converter with adaptive noise reduction
A content-dependent scan rate converter with adaptive noise reduction that provides a highly integrated, implementation efficient de-interlacer. By identifying...
US-7,375,664 Systems and methods for providing anti-aliasing in a sample-and-hold circuit
Systems and methods are included for providing anti-aliasing in a sample-and-hold circuit. One embodiment of the present invention includes a method for sampling...
US-7,375,599 Analog circuit and method for multiplying clock frequency
A signal generating circuit includes a relaxation oscillator operating to alternately generate a first ramp signal that is periodic at a frequency of the...
US-7,375,598 System and method for increasing radio frequency (RF)/microwave inductor-capacitor (LC) oscillator frequency...
System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. A preferred embodiment comprises a voltage controlled oscillator...
US-7,375,586 Low voltage structure for gain boosting in high gain amplifiers
Reducing the bias voltage level required in a boost amplifier enhancing a gain of amplifier comprising first and second amplification stages. In an embodiment,...
US-7,375,585 Circuit and method for switching active loads of operational amplifier input stage
An operational amplifier having a wide input common mode voltage range includes first (2) and second (3) differential input transistor pairs coupled to first...
US-7,375,567 Digital storage element architecture comprising dual scan clocks and preset functionality
A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and...
US-7,375,471 Charging circuit
A charging circuit has a battery 12, switching element 14, and resistor 16 for current detection arranged on the primary side of transformer 10. Diode 18 and...
US-7,374,866 System and method for exposure of partial edge die
According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a photoresist layer on a surface of a wafer....
US-7,374,080 System and method for securing the initialization of an inherently non-secure Smartcard controller
A system and method for securing the initialization of a Smartcard controller and a Smartcard terminal incorporating the system or the method. In one embodiment,...
US-7,373,571 Achieving desired synchronization at sequential elements while testing integrated circuits using sequential...
A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated...
US-7,373,437 Multi-channel DMA with shared FIFO
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with "m" threads...
US-7,372,922 RSSE optimization using hardware acceleration
A Reduced State Sequence Equalizer (RSSE) is implemented using a butterfly hardware accelerator (58) in the form of a butterfly to increase the efficiency of...
US-7,372,890 Methods and systems for detecting and mitigating interference for a wireless device
In at least some embodiments, a method for mitigating interference between an Ultra Wideband (UWB) device and a non-UWB device is provided. The method includes,...
US-7,372,837 Incremental redundancy using two stage rate matching for automatic repeat request to obtain high speed transmission
Methods and apparatus for processing a data stream for high speed wireless Transmission. At the transmission side, the methods and apparatus rate-match an...
US-7,372,825 Wireless communications system with cycling of unique cell bit sequences in station communications
A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver...
US-7,372,713 Match sensing circuit for a content addressable memory device
A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match...
US-7,372,649 Apparatus and method for applying write signals for driving a write head
An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first...
US-7,372,507 Real-time content based gamma adjustment for digital video display
Methods for improving video images by making real-time gamma correction adjustments to such images are described. More particularly, gamma correction adjustments...
US-7,372,387 Digital-to-analog converter with triode region transistors in resistor/switch network
System and method for high-speed and high-precision digital to analog conversion. A preferred embodiment comprises a dual-resistor ladder digital-to-analog...
US-7,372,381 Programmable serializer for a video display
A serializer receives parallel data and a control signal. The serializer splits the parallel data into multiple subportions of data and, based on the control...
US-7,372,340 Precision frequency and phase synthesis with fewer voltage-controlled oscillator stages
A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a...
US-7,372,307 Efficient current monitoring for DC-DC converters
A current monitoring circuit for DC-DC switching converters includes a track and latch comparator circuit (30) having a preamplifier (32) that is controlled...
US-7,372,240 Output load adaptable MOSFET gate drive voltage level in a DC-DC controller
The output current of a fixed-frequency DC to DC converter is sensed, creating a voltage representative of the load current. This voltage is then compared to one...
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