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Integration of pore sealing liner into dual-damascene methods and devices
A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is...
Method for manufacturing a semiconductor device having a silicided gate
electrode and a method for...
The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor...
Method for manufacturing dual work function gate electrodes through local
The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first...
Semiconductor packages for enhanced number of terminals, speed and power
An integrated circuit device package with a first part (101) having a cavity (104) to mount the chip (105), further I/O terminals (102) on the top surface and...
Pressure glow plug for a diesel engine
A pressure glow plug for a diesel engine has a glow plug body 2 for being inserted into a cylinder of the diesel engine, a heating rod 1 that is arranged in the...
System and method for power profiling of tasks
Systems and methods for improved power profiling of embedded applications are presented. These inventions provide the ability to measure the power consumption of...
Optical assembly having cylindrical lenses and related method of
modulating optical signals
Described embodiments provide for an optical communications assembly or other optical assembly in which the post-dispersion optical signals are controlled in...
Enhanced color correction circuitry capable of employing negative RGB
Disclosed is a system for adjusting a plurality of component color signals for expanded color gamut displays. The disclosed system comprises an input for...
System and method for ranging
A system operable for ranging synchronization is provided. The system includes a first component that is operable to analyze a set of signals. The first...
Method and apparatus for CDMA demodulation
A CDMA receiver (500) minimizes the use of hardware by taking advantage of the fact that Walsh sequences of a predetermined length (e.g., 16) are comprised of...
Method and apparatus for increasing a perceived resolution of a display
According to one embodiment, a method of increasing a perceived resolution of a display includes directing light at a optical dithering element and repeatedly...
Silicide formation using a low temperature anneal process
A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer...
Method for fabricating low resistance, low inductance interconnections in
high current semiconductor devices
A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a...
Method and apparatus for lubricating microelectromechanical devices in
The present invention provides a lubricant container inside a microelectromechanical device package. The lubricant container contains selected lubricant that...
Real-time monitoring, alignment, and translation of CPU stalls or events
A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code...
Method for calibrating automatic gain control in wireless devices
Disclosed herein is an iterative process for calibrating an AGC in a wireless system, wherein the iterative process includes transmitting a calibration signal,...
Variable block rate ADSL
By allowing the block rate to vary, the existing Asymmetric Digital Subscriber Line (ADSL) system is modified to better address extended reach and higher data...
Static random access memory device having reduced leakage current during
active mode and a method of operating...
An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row...
Resampling methods for digital images
Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage...
Gate leakage insensitive current mirror circuit
A gate leakage insensitive current mirror circuit including an input stage, an output stage, and a pair of complementary source followers. The pair of...
Double-edge, stackable PWM with built-in feedforward
A method and apparatus for use in a multi-phase power system. The power system is of the type having a plurality of Pulse Width Modulation (PWM) controllers...
Simultaneous deposition and etch process for barrier layer formation in
microelectronic device interconnects
The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is...
Microprocessor with independent SIMD loop buffer
An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of...
Management of stack-based memory usage in a processor
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from...
System and method for power efficient memory caching
A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an...
Wideband speech coding with modulated noise highband excitation system and
A speech encoder/decoder for wideband speech with a partitioning of wideband into lowband and highband, convenient coding of the lowband, and LP excited by noise...
A method of image compression with non-redundant complex wavelet transforms applied using a triband decomposition. Variant transforms for real and complex inputs...
Method and apparatus for low power-rise power control using
sliding-window-weighted QoS measurements
A system and method for adjusting the power control target for a spread-spectrum communication system 110 is disclosed. A preferred embodiment comprises...
Optical system and method for increasing image resolution and/or dithering
in projection applications
An optical system for projecting an image having x and y axes onto a image plane is provided. The system includes an SLM device spaced from the image plane, the...
Digital still camera system and complementary-color-filtered array
A complementary-color-filtered array interpolation by first interpolate each color subarray so each pixel has four colors and then adjust each color at a pixel...
Interleaved analog to digital converter with compensation for parameter
mismatch among individual converters
Interleaved analog to digital converter with compensation for parameter mismatch among individual converters. A reference ADC samples an input signal at...
Oscillator system, method of providing a resonating signal and a
communications system employing the same
An n.sup.th-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment,...
Method and apparatus for rapid local oscillator frequency calibration
A controller for an adjustable-frequency oscillator includes a first counter supplied with a stop-count value to count adjustable-frequency oscillator cycles...
Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores...
Addressable tap domain selection circuit with selectable 3/5 pin interface
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
Maintaining synchronization of multiple data channels with a common clock
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g.,...
Branch prediction and other processor improvements using FIFO for
bypassing certain processor pipeline stages
A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken...
Clock divider with glitch free dynamic divide-by change
The circuit of this invention performs clock division with dynamic divide-by value change capability. This circuit provides low area and low latency. The clock...
Generalized envelope matching technique for fast time-scale modification
A time-domain time-scale modification method based on the synchronous overlap-and-add method consists of a generalization of the envelope-matching time-scale...
High order trans-impedance filter with a single operational amplifier
A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor,...
Alternate method of showing commercials using personal video recorders
A recording and playback system comprising a personal video recorder ("PVR") coupled to a television monitor. The PVR records a video broadcast stream which...
A method of image compression with wavelet transforms applied locally rather than globally by image component partitioning into independently transformed...
Forward compatibility hooks for DFS and TPC for WLAN
A method provides forward compatibility hooks for DFS and TPC for WLAN, so that the same mechanisms can be employed (with only minor changes/additions) for other...
Method and apparatus for accessing a plurality of devices using a single
A method for accessing a plurality of devices by a system using a single communication port communicatively coupled with each respective device of the plurality...
High performance, low leakage SRAM device and a method of placing a
portion of memory cells of an SRAM device...
An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a...
Staggered memory cell array
A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also...
Home picture/video display system with ultra wide-band technology
A new display system and method is described, utilizing a cellular telephone having digital camera capability and a television linked directly over a UWB...
Selectable application of offset to dynamically controlled voltage supply
An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage...
Operations with logical states from a four voltage level signal
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
Analog built-in self-test module
An analog BIST (Built-in Self-Test) module for a load board in a test system for testing Integrated Chips (IC) and other devices-under-test (DUTs). Components of...