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Patent # Description
US-7,333,141 Resampling methods for digital images
Polyphase filtering, such as resampling for image resizing, on a processor with parallel output units is cast in terms of data access blocks and data coverage...
US-7,332,965 Gate leakage insensitive current mirror circuit
A gate leakage insensitive current mirror circuit including an input stage, an output stage, and a pair of complementary source followers. The pair of...
US-7,332,898 Double-edge, stackable PWM with built-in feedforward
A method and apparatus for use in a multi-phase power system. The power system is of the type having a plurality of Pulse Width Modulation (PWM) controllers...
US-7,332,425 Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects
The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is...
US-7,330,964 Microprocessor with independent SIMD loop buffer
An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of...
US-7,330,937 Management of stack-based memory usage in a processor
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from...
US-7,330,936 System and method for power efficient memory caching
A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an...
US-7,330,814 Wideband speech coding with modulated noise highband excitation system and method
A speech encoder/decoder for wideband speech with a partitioning of wideband into lowband and highband, convenient coding of the lowband, and LP excited by noise...
US-7,330,597 Image compression
A method of image compression with non-redundant complex wavelet transforms applied using a triband decomposition. Variant transforms for real and complex inputs...
US-7,330,504 Method and apparatus for low power-rise power control using sliding-window-weighted QoS measurements
A system and method for adjusting the power control target for a spread-spectrum communication system 110 is disclosed. A preferred embodiment comprises...
US-7,330,298 Optical system and method for increasing image resolution and/or dithering in projection applications
An optical system for projecting an image having x and y axes onto a image plane is provided. The system includes an SLM device spaced from the image plane, the...
US-7,330,209 Digital still camera system and complementary-color-filtered array interpolation method
A complementary-color-filtered array interpolation by first interpolate each color subarray so each pixel has four colors and then adjust each color at a pixel...
US-7,330,140 Interleaved analog to digital converter with compensation for parameter mismatch among individual converters
Interleaved analog to digital converter with compensation for parameter mismatch among individual converters. A reference ADC samples an input signal at...
US-7,330,082 Oscillator system, method of providing a resonating signal and a communications system employing the same
An n.sup.th-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment,...
US-7,330,079 Method and apparatus for rapid local oscillator frequency calibration
A controller for an adjustable-frequency oscillator includes a first counter supplied with a stop-count value to count adjustable-frequency oscillator cycles...
US-7,328,388 Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores...
US-7,328,387 Addressable tap domain selection circuit with selectable 3/5 pin interface
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,328,360 Maintaining synchronization of multiple data channels with a common clock signal
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g.,...
US-7,328,332 Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages
A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken...
US-7,328,229 Clock divider with glitch free dynamic divide-by change
The circuit of this invention performs clock division with dynamic divide-by value change capability. This circuit provides low area and low latency. The clock...
US-7,328,076 Generalized envelope matching technique for fast time-scale modification
A time-domain time-scale modification method based on the synchronous overlap-and-add method consists of a generalization of the envelope-matching time-scale...
US-7,327,997 High order trans-impedance filter with a single operational amplifier
A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor,...
US-7,327,931 Alternate method of showing commercials using personal video recorders
A recording and playback system comprising a personal video recorder ("PVR") coupled to a television monitor. The PVR records a video broadcast stream which...
US-7,327,894 Image compression
A method of image compression with wavelet transforms applied locally rather than globally by image component partitioning into independently transformed...
US-7,327,763 Forward compatibility hooks for DFS and TPC for WLAN
A method provides forward compatibility hooks for DFS and TPC for WLAN, so that the same mechanisms can be employed (with only minor changes/additions) for other...
US-7,327,751 Method and apparatus for accessing a plurality of devices using a single communication port
A method for accessing a plurality of devices by a system using a single communication port communicatively coupled with each respective device of the plurality...
US-7,327,598 High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device...
An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a...
US-7,327,591 Staggered memory cell array
A method of placing a cell in an array is disclosed. The method includes placing the cell a plurality of times (600, 602, 604) in a first array. The cell is also...
US-7,327,385 Home picture/video display system with ultra wide-band technology
A new display system and method is described, utilizing a cellular telephone having digital camera capability and a television linked directly over a UWB...
US-7,327,185 Selectable application of offset to dynamically controlled voltage supply
An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage...
US-7,327,162 Operations with logical states from a four voltage level signal
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
US-7,327,153 Analog built-in self-test module
An analog BIST (Built-in Self-Test) module for a load board in a test system for testing Integrated Chips (IC) and other devices-under-test (DUTs). Components of...
US-7,327,035 System and method for providing a low frequency filter pole
Systems are provided for producing a low frequency filter pole. A first bond pad is coupled to a power source. A second bond pad is inductively connected to the...
US-7,326,918 Optical position sensor architecture for servo systems
System and method for an optical position sensor architecture for use in servo systems. A preferred embodiment comprises a light source configured to produce a...
US-7,326,025 System for detecting warped carriers and associated methods
Disclosed herein is a warp detection system (200) for determining warping in a carrier (110) configured to carry substrates (120) for processing. In one...
US-7,325,209 Using patterns for high-level modeling and specification of properties for hardware systems
This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation...
US-7,325,178 Programmable built in self test of memory
The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g....
US-7,325,169 Apparatus and method for trace stream identification of multiple target processor events
When a plurality of simultaneous, preselected target processor events are detected, a multiple-event sync marker is generated that identifies the preselected...
US-7,324,914 Timing closure for system on a chip using voltage drop based standard delay formats
A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple...
US-7,324,614 High speed decoder
A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high...
US-7,324,602 Scalable time-orthogonal preamble supplement generator, method of generating and multiple-input,...
The present invention provides a time-orthogonal preamble supplement generator for use with a multiple-input, multiple-output (MIMO) transmitter employing N...
US-7,324,585 System and method for performing symbol boundary-aligned search of direct sequence spread spectrum signals
System and method for performing symbol boundary aligned searches of signals. A preferred embodiment comprises a search control unit (such as search control unit...
US-7,324,485 Random access preamble coding for initiation of wireless mobile communications sessions
A method of operating a wireless communications unit (UE) to request a connection with a base station (10) is disclosed. The wireless unit (UE) receives a signal...
US-7,324,392 ROM-based memory testing
This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the...
US-7,324,391 Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real...
A method (200) for determining various bit failure modes in a static random access memory device. A hard/soft bit failure test sequence is performed on each cell...
US-7,324,279 Dual modulator projection system
A three dimensional display system 100 using two spatial light modulators and a single projection path. Light source 102 emits a white light beam 104 which...
US-7,324,229 Rendering in a printer using bands
A page may be divided into several blocks which do not span the entire width of a page. A bit map representing the page content may be generated by rendering the...
US-7,323,917 Method and apparatus for synthesizing a clock signal having a frequency near the frequency of a source clock signal
An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a...
US-7,323,899 System and method for resumed probing of a wafer
According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set...
US-7,323,793 System and method for driving one or more loads
A system and method for driving a load at a desired operating level. A driver is connected to a load. The load can be selected from a plurality of loads by a...
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