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Patent # Description
US-7,323,899 System and method for resumed probing of a wafer
According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set...
US-7,323,793 System and method for driving one or more loads
A system and method for driving a load at a desired operating level. A driver is connected to a load. The load can be selected from a plurality of loads by a...
US-7,323,751 Thin film resistor integration in a dual damascene structure
A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer....
US-7,323,727 System with meshed power and signal buses on cell array
A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a...
US-7,323,409 Method for forming a void free via
A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier...
US-7,323,405 Fine pitch low cost flip chip substrate
A method of forming a package is disclosed, which includes steps of forming a substrate, a solder masker, and a first aperture through the solder mask. The...
US-7,323,403 Multi-step process for patterning a metal gate electrode
The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method...
US-7,323,362 Manufacturing system and apparatus for balanced product flow with application to low-stress underfilling of...
A system (100) for manufacturing product, in which a first work station (101) is operable to perform a first manufacturing action on the product parts; this...
US-7,321,980 Software power control of circuit modules in a shared and distributed DMA system
A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable...
US-7,321,912 Device with dB-to-linear gain conversion
An electronic dB-to-linear gain conversion system (10). The system comprises an input (12) for receiving a gain index signal (GI) representing a desired dB...
US-7,321,836 Method for determining the equivalency index of goods, processes, and services
A method is disclosed wherewith a person skilled in the art of statistical quality control may determine whether a process, goods, or service is statistically...
US-7,321,784 Method for physically updating configuration information for devices in a wireless network
A method for providing configuration information for use in installing a new wireless station to a wireless network that minimizes errors is presented. The...
US-7,321,644 Low-complexity, symbol-based, reduced substreams maximum likelihood decoder and method for a multiple-input,...
A greater likelihood decoder, a method of deriving a reduced substreams maximum likelihood (RSML) decoded symbol vector and a multiple-input, multiple-output...
US-7,321,618 PCM upstream data transmission server
A method for designing an equalizer and tracking performance for upstream PCM in a digital communications network is described. The invention optimizes upstream...
US-7,321,568 Realtime management of processing resources
The invention presents a software agent that optimizes processing resources for multiple instances of a software module that are executing simultaneously. The...
US-7,321,564 Hybrid IMMSE-LMMSE receiver processing technique and apparatus for a MIMO WLAN
A Hybrid IMMSE-LMMSE receiver processing technique predicts performance of and selects between iterative and non-iterative decoding of symbols based on an...
US-7,321,458 Apparatus for controlling the positioning of an optical dithering element
According to one embodiment, a method for controlling positioning of an optical dithering element includes repeatedly driving the optical dithering element...
US-7,321,154 Refractory metal-based electrodes for work function setting in semiconductor devices
The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate...
US-7,320,927 In situ hardmask pullback using an in situ plasma resist trim process
The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a...
US-7,320,903 Apparatus for and method of packaging semiconductor devices
A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one...
US-7,319,701 Modem relay protocol redundancy for reliable low speed modem communications over IP networks with substantial...
Minimized Wave-zone Buoyancy is a new approach to oil and gas platform design with superior construction and performance characteristics compared to state-of-art...
US-7,319,419 Switched capacitor circuit with current source offset DAC and method
A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational...
US-7,319,357 System for controlling switch transistor performance
The present invention provides a system for controlling performance of a switch transistor (106)--one that is implemented within a circuitry segment (100) to...
US-7,319,354 Signal processing apparatus having internal clock signal source
A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock...
US-7,319,275 Adhesion by plasma conditioning of semiconductor chip
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-7,318,208 Method for circuit sensitivity driven parasitic extraction
The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at...
US-7,318,176 Tracing program counter addresses using native program counter format and instruction count format
A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter...
US-7,318,112 Universal interface simulating multiple interface protocols
A universal interface interfaces between a variety of different data processing devices by the generation, storage, proper routing, and timed output of data...
US-7,318,017 Collecting and exporting on-chip data processor trace and timing information with differing collection and...
Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is...
US-7,317,776 Efficient pseudo-noise sequence generation for spread spectrum applications
The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used,...
US-7,317,760 System and method for finger and path management in receivers
System and method for managing finger and path resources. A preferred embodiment comprises receiving a delay profile, processing paths from the delay profile,...
US-7,317,355 Over-current detection for a power field-effect transistor (FET)
A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection...
US-7,315,992 Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation...
US-7,315,971 Systems and methods for improved memory scan testability
A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the...
US-7,315,905 Software controlled hard reset of mastering IPS
A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a...
US-7,315,879 Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and...
A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate...
US-7,315,808 Correlating on-chip data processor trace information for export
In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a...
US-7,315,806 Enhanced negative constraint calculation for event driven simulations
A technique to enable accurate timing and functional verification in a negative constraint calculation (NCC) implemented event-driven logic simulators when there...
US-7,315,601 Low-noise sigma-delta frequency synthesizer
A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding...
US-7,315,596 Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability
The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to...
US-7,315,573 Channel monitoring for improved parameter selection in a communication system
A method is provided for automatically improving throughput of an active channel in a communication system comprising: receiving input from one or more modules...
US-7,315,540 Random access memory based space time switch architecture
A data switching circuit (10). The data switching circuit comprises at least one input (10.sub.in) for receiving during a same time period a plurality of data...
US-7,315,294 Deinterleaving transpose circuits in digital display systems
The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the...
US-7,315,261 Method for converting data from pixel format to bitplane format
This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform...
US-7,315,191 Digital storage element architecture comprising dual scan clocks and reset functionality
A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and...
US-7,315,183 Single-supply voltage translator input having low supply current
A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a...
US-7,315,182 Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode...
A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential...
US-7,314,816 Masking layer in substrate cavity
A package that resists creation of particles in a package cavity. A package according to one embodiment of the present invention contains a mechanical device...
US-7,314,800 Application of different isolation schemes for logic and embedded memory
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and...
US-7,313,705 Implementation of a secure computing environment by using a secure bootloader, shadow memory, and protected memory
A computer system with a secure bootloading function is disclosed. Security logic (20) is implemented on-chip with a central processing unit (CPU) (10), and...
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