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Patent # Description
US-9,435,860 Gated state machine circuitry having three clock 2 enable states
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test...
US-9,435,859 Interposer capture shift update cell between functional and test data
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement...
US-9,432,654 Modifying fusion offset data in sequential stereoscopic image frames
The present invention is drawn to a device for use with first stereoscopic data, second stereoscopic data and a display device. The device includes an input...
US-9,432,576 Method and apparatus for fusing images from an array of cameras
An image fusing method, apparatus and system for fusing images from an array of cameras, method includes selecting a camera from the array of cameras as a...
US-9,432,196 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices
A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first...
US-9,432,163 Pseudorandom sequence generation for OFDM cellular systems
In one embodiment, a transmitter includes a binary sequence generator unit configured to provide a sequence of reference signal bits, wherein the sequence is an...
US-9,432,077 DSSS preamble detection for smart utility networks
Embodiments of the invention provide a method to detect DSSS preambles in smart utility networks. A DSSS signal is received by a receiver and a digital sequence...
US-9,432,044 Mismatch correction of attenuation capacitor in a successive approximation register analog to digital converter
A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) is calibrated by determining an error voltage for each of a plurality...
US-9,431,947 Input vector set for position detection of PM motors
A method of determining angular position (A) of a rotor of an N-phase permanent magnet motor (PMM). A processor having an associated stored angular position...
US-9,431,945 Normalization of motor phase measurements
A method of normalizing phase measurements for a motor using a normalizing phase measurements (NPM) algorithm that a processor implements to cause a motor...
US-9,431,896 Apparatus and method for zero voltage switching in bridgeless totem pole power factor correction converter
Power factor correction (PFC) apparatus, controllers, and methods for operating bridgeless totem pole power factor correction converters in which AC input...
US-9,431,533 Method to enable higher carbon co-implants to improve device mismatch without degrading leakage
An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo...
US-9,431,509 High-K metal gate
An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer...
US-9,431,480 Diluted drift layer with variable stripe widths for power transistors
A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift...
US-9,431,384 Programmable ESD protection circuit
An electrostatic discharge (ESD) protection circuit (FIG. 5A) for an integrated circuit is disclosed. The integrated circuit includes a first ESD cell having a...
US-9,431,302 Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
US-9,431,286 Deep trench with self-aligned sinker
A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench...
US-9,431,253 Fabrication flow based on metal gate process for making low cost flash memory
An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions...
US-9,431,248 High tilt angle plus twist drain extension implant for CHC lifetime improvement
An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one...
US-9,430,393 System and method for managing cache
A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter...
US-9,430,346 Processor power measurement
A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The...
US-9,430,008 Apparatus and method for optimizing use of NVDC chargers
A method includes detecting removal or depletion of a power supply associated with a powered device. The powered device is configured to receive power from a...
US-9,429,971 Short-circuit protection for voltage regulators
Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error...
US-9,429,968 Power-gated electronic device
A power-gated electronic device and a method of operating the same is provided. The power-gated electronic device comprises a low drop out voltage power supply...
US-9,429,918 Atomic clocks and magnetometers with vapor cells having condensation sites in fluid communication with a cavity...
A vapor cell for installation in an atomic clock or a magnetometer. The vapor cell includes a top plate, a center plate, and a bottom plate defining a cavity...
US-9,429,645 Programmable wavelet tree
An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to...
US-9,429,528 Determining gas absorption line from separate and alternating RF signals
A method to detect a gas absorption line that includes alternately transmitting and sweeping two radio frequency (RF) signals through an absorption cell,...
US-9,426,458 Video output supervisor
A video output supervisor includes a test region indicator for verifying that the commanded output to specific areas of a display is valid. Areas reserved...
US-9,425,955 Power line communication (PLC) network nodes using cipher then segment security
Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates...
US-9,425,871 4TX codebook enhancement in LTE
Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based...
US-9,425,811 Method and apparatus for compensating offset drift with temperature
The disclosure provides an analog to digital converter (ADC). The ADC includes a comparator that receives a threshold voltage. A set of elementary capacitors is...
US-9,425,808 Frequency detector
A frequency detection technique includes generating first and second signals such that a frequency of the first signal is the same as a frequency of the second...
US-9,425,792 Reconfigurable power switch chains for efficient dynamic power saving
Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for...
US-9,425,771 Low area flip-flop with a shared inverter
A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock...
US-9,425,739 Tunable quadrature oscillator
A tunable quadrature oscillator includes a first oscillator having an output, a second oscillator having an output, and a variable gain amplifier. The variable...
US-9,425,188 Active ESD protection circuit with blocking diode
An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a...
US-9,425,132 Stacked synchronous buck converter having chip embedded in outside recess of leadframe
A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor...
US-9,424,193 Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
US-9,423,808 DC to DC converter with pseudo constant switching frequency
A method for a DC to DC converter with a pseudo constant switching frequency is disclosed herein. For example, some embodiments provide a DC to DC converter...
US-9,423,459 Taps with class T0-T2 and T3, T4(W), and T5(W) capabilities
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
US-9,423,458 Transporting ordered test data, mode select, ready, precharge packet bits
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to...
US-9,419,903 Structure for implementing openflow all group buckets using egress flow table entries
An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets....
US-9,419,835 System and method for preamble detection in MIMO narrowband power line communications
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
US-9,419,788 Data transfer clock recovery for legacy systems
The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate...
US-9,419,750 NLOS wireless backhaul uplink communication
A method for uplink (UL) wireless backhaul communication at a wireless backhaul remote unit in a radio access network comprising receiving a configuration for...
US-9,419,630 Phase shifted coarse/fine clock dithering responsive to controller select signals
A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an...
US-9,419,613 Low power scheme to protect the low voltage capacitors in high voltage IO circuits
An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being...
US-9,419,594 Clock data recovery system
A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal;...
US-9,419,591 Controllable wide frequency range oscillator
A circuit includes a ring oscillator that includes a plurality of delay stages coupled in series to generate an output frequency for the ring oscillator. A...
US-9,419,509 Shared bootstrap capacitor for multiple phase buck converter circuit and methods
A multiple phase dc to dc converter with a shared bootstrap capacitor. In an embodiment, a multiple phase buck converter is disclosed including a plurality of n...
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