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Stator resistance estimation for electric motors
A method of controlling an electric motor (motor) includes providing a processor having an associated memory storing a stator resistance (Rs) estimation (RSE)...
Electronic device for average current mode DC-DC conversion
An average current mode buck-boost DC to DC converter has a buck stage coupled between an input voltage source terminal and an output terminal. A boost stage is...
Droop reduction circuit for charge pump buck converter
A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a...
Motor fault detector
A motor control circuit includes a processor configured to calculate a plurality of motor impedances from measurements of an excitation voltage on a power bus...
Integration of the silicon IMPATT diode in an analog technology
A method to integrate a vertical IMPATT diode in a planar process.
MOSFET with source side only stress
An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement...
Integration of analog transistor
An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of...
Low-cost CMOS structure with dual gate dielectrics and method of forming
the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
SRAM with buffered-read bit cells and its testing
An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a...
Adaptive environmental context sample and update for comparing speech
A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sparse sound parameter information is...
First and second data communication circuitry operating in different
Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and...
Method and circuitry for regulating a voltage
In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target...
Low cost window production for hermetically sealed optical packages
Disclosed embodiments demonstrate batch processing methods for producing optical windows for microdevices. The windows protect the active elements of the...
Test messaging demodulate and modulate on separate power pads
The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device....
High voltage polymer dielectric capacitor isolation device
An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed...
Fast locking clock and data recovery using only two samples per period
A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are...
Codebook sub-sampling for CSI feedback on PUCCH for 4Tx MIMO
Channel state information (CSI) feedback in a wireless communication system is disclosed. User equipment transmits a CSI feedback signal via a Physical Uplink...
Interference mitigation detector encompassing high power peak integer chip
A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes...
Systems for accurate multiplexing
The disclosure presented herein provides example embodiments of systems for accurate multiplexing. The systems and methods presented may be suitable for...
System and method for pulse width modulation
A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has...
Spacer shaper formation with conformal dielectric film for void free PMD
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
Field effect transistor and method of making
A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the...
Silicide formation due to improved SiGe faceting
An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the...
Ultraviolet energy shield for non-volatile charge storage memory
An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing....
Locking/unlocking CPUs to operate in safety mode or performance mode
An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to...
High-temperature isotropic plasma etching process to prevent electrical
A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an...
Microstrip line of different widths, ground planes of different distances
An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and...
Test clock/test mode slect (TCK/TMS), select, data register (DR)
connection circuitry between test access port...
An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a...
Inductive position sensing with single channel interface to multiple
An inductive sensing system includes multiple resonant sensors interfaced to an inductance-to-digital conversion (IDC) unit through a single channel interface....
Method for determining the location of control channels in the uplink of
Embodiments of the invention provide methods for user equipments to implicitly determine the location for the transmission of uplink control signaling...
Flexible scrambler/descrambler architecture for a transceiver
An apparatus is provided. A polynomial register having a plurality of bits is provided, where the polynomial register is configured to store a user-defined...
Method and apparatus for channel state information feedback in a
coordinated multi-point communication system
A method of operating a wireless communication system (FIG. 4) is disclosed. The method includes receiving a plurality of reference signals from a respective...
Autoconfigurable phase-locked loop which automatically maintains a
constant damping factor and adjusts the loop...
A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating...
Binary frequency shift keying with data modulated in digital domain and
carrier generated from intermediate...
Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock...
System and method for single phase transition for multiphase DCDC
A DCDC converter includes a controller, an up/down counter, a first power stage and a second power stage. The controller generates an up/down control signal....
Poly sandwich for deep trench fill
A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon...
Epitaxial source/drain differential spacers
A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over...
Dual mode ferroelectric random access memory (FRAM) cell apparatus and
methods with imprinted read-only (RO) data
Read-only ("RO") data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as...
Tracking energy consumption using a boost-buck technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
Method, system and apparatus for intra-prediction in video signal
processing using combinable blocks
A method, apparatus and system for a video encoder for selecting a block of intermediate size from a set of block sizes for intra-prediction estimation for...
Shared-field image projection and capture system
According to one embodiment of the present invention a method for capturing images on a screen is disclosed. The method includes directing light from a surface...
Gear shifting from binary phase detector to PAM phase detector in CDR
A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM)...
Partial CQI feedback in wireless networks
Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an...
Asynchronous analog-to-digital converter
An asynchronous analog-to-digital converter (AADC) and a method of using the AADC are shown. The AADC includes a digital-to analog-converter (DAC), a...
Hybrid digital-to-analog conversion system
A digital-to-analog conversion (DAC) circuit has a resistor ladder circuit controlled by high order bits and a resistor string circuit controlled by low order...
Sensor with low power model based feature extractor
Described examples include low power analog front end circuits for sensing repeating signal waveforms, including a first sampling circuit to sample an input...
Shared divide by N clock divider
A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division...
Sensed motor winding current adapting blanking period between max/min
Stepper motor winding current regulation methods and apparatus adapt a maximum blanking period to generate an adapted blanking period that is proportional to a...
BLDC motor sinusoidal PWM with single phase BEMF slot detection
A back electromotive force (BEMF) zero cross may be detected in a brushless direct current (BLDC) motor that is controlled by pulse width modulation (PWM). A...
DC-DC switching regulator with transconductance boosting
A switching regulator comprising a droop amplifier responsive to a reference voltage and a feedback voltage to generate a droop voltage. The droop amplifier...