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Patent # Description
US-7,360,060 Using IMPDEP2 for system commands related to Java accelerator hardware
A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set...
US-7,359,813 Outlier screening technique
Multiple parameters of manufactured units are continually measured until some of the units fail, where failure can be accelerated by adjusting operating...
US-7,359,684 Wireless communication system with variable intermediate frequency transmitter
A wireless communication device (UST), comprising an input for receiving baseband data (I, Q) in a first signal having a first frequency. The device also...
US-7,359,430 CDMA multicode channel processing
A demodulator such as a Fast Hadamard Transform (FHT) based demodulator is used to demodulate all channels in a code space with code length equal to the data...
US-7,359,409 Packet loss concealment for voice over packet networks
A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals....
US-7,359,173 System and method for protecting IC components
One embodiment provides a system for protecting at least one component in an integrated circuit (IC). The system includes a disconnect element that is...
US-7,359,107 Analog MEMS with non-linear support
The disclosed embodiments reveal an analog MEMS device with a pivotal micromirror that is supported by one or more beams that provide non-linear resistance. An...
US-7,358,801 Reducing noise and/or power consumption in a switched capacitor amplifier sampling a reference voltage
Equal common mode voltage is present at the input terminals of an operational amplifier with amplifies the residue signal in a stage of an ADC in two phases...
US-7,358,617 Bond pad for ball grid array package
A device (100) and a method (200) for controlling resin bleed, the device comprising a substrate (105) having a surface (107), an integrated circuit (115) having...
US-7,356,745 IC with parallel scan paths and compare circuitry
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections....
US-7,356,624 Interface between different clock rate components
A circuit for interfacing between a first component 11 operating at a first clock rate and a second component 12 operating at a second clock rate, wherein the...
US-7,356,424 Diagnostic compiler for pipeline analog-to-digital converter, method of compiling and test system employing the...
The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to...
US-7,356,107 Flying-adder frequency synthesizer-based digital-controlled oscillator and video decoder including the same
A video decoder (52, 152) including a digital-control oscillator (DCO) (60, 160) is disclosed. The DCO (60, 160) includes a first flying-adder frequency...
US-7,356,088 M-dimension M-PAM trellis code system and associated trellis encoder and decoder
An M-dimension M-PAM trellis code encoder, a method of encoding user bits and a decoder. In one embodiment, the encoder includes: (1) a convolutional encoder...
US-7,356,069 Spread spectrum demodulation using a subsampling communication receiver architecture
A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, ....
US-7,356,021 Increasing the throughput of voice over internet protocol data on wireless local area networks
A system and method are provided for improving the throughput of wireless networks, such as IEEE 802.11 networks. Individual devices in the network determine the...
US-7,355,976 Method and apparatus for providing retry control, buffer sizing and management
A retry algorithm determines the maximum number of transmissions and retransmissions that may be attempted for the frame in the head of a transmit queue or...
US-7,355,777 Energy storage structures using electromechanically active materials for micro electromechanical systems
System and method for storing energy using electromechanically active materials in micro electromechanical systems. A preferred embodiment comprises a movable...
US-7,355,655 Systems and methods for separating luma and chroma information in a composite video signal
Systems and method are provided for luma-chroma separation. A demodulator system demodulates a composite video signal to produce at least two baseband chroma...
US-7,355,430 Parallel scan distributors and collectors and process of testing integrated circuits
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-7,355,255 Nickel silicide including indium and a method of manufacture therefor
The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same....
US-7,354,865 Method for removal of pattern resist over patterned metal having an underlying spacer layer
A method of removing the pattern resist that remains on a microchip wafer after etching a patterned layer that is supported by a spacer layer. After the etch,...
US-7,354,854 Nickel silicide method and structure
Nickel silicide contact regions are formed on a source (2), drain (3) and polycrystalline silicon gate (5) of an integrated circuit transistor by annealing it...
US-7,354,853 Selective dry etching of tantalum and tantalum nitride
The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in...
US-7,353,307 Linking addressable shadow port and protocol for serial bus networks
Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of...
US-7,353,217 Intelligent realtime management of processing resources
A method and system for ordering a priority for a function to receive any type of processing resources in a system that includes a plurality of functions. The...
US-7,352,823 Algorithm for computing distances to a received point in an ADSL system
Method for computing distances to received data points. A preferred embodiment comprises determining a first point on a grid nearest to the received point,...
US-7,352,820 DMT system with variable subchannel spacing in TCM ISDN noise
A device comprises a first component operable to produce a plurality of discrete multitone symbols based in part on a subchannel spacing and a cyclic extension...
US-7,352,818 Short and long sequence boundary detection algorithm for wireless LAN modems
A method for detecting a boundary between two sequences in a wireless local area network is presented that permits rapid detection of the boundary. The method...
US-7,352,801 Selecting one of multiple antennas to receive signals in a wireless packet network
Selecting one of multiple antennas to receive signals in a wireless packet network. Correlation value and gain needed to boost the signal up to a desired power...
US-7,352,691 Double difference phase detection
A method that allows a digital communications system to detect the presence of transmitted messages in noisy environments. The system includes an OFDM...
US-7,352,251 Systems and methods for suppressing feedback and reference noise in a phase lock loop circuit
Various systems and methods for clock management. As one example, a system for clock management is disclosed that includes a controllable oscillator, an...
US-7,352,231 Method and circuit for perturbing removable singularities in coupled translinear loops
A translinear network (34) has first (Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4) and second (Q.sub.4, Q.sub.3, Q.sub.5, Q.sub.6) translinear loops. A Trafton-Hastings...
US-7,352,228 Method and apparatus of a level shifter circuit with duty-cycle correction
A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to...
US-7,352,169 Testing components of I/O paths of an integrated circuit
Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal...
US-7,352,161 Burst-mode switching voltage regulator with ESR compensation
System and method for a burst-mode switching voltage regulator with good stability and small output voltage ripple. A preferred embodiment comprises a current...
US-7,351,651 Structure and method for contact pads having a recessed bondable metal plug over of copper-metallized...
A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the...
US-7,351,632 Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride...
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS...
US-7,351,626 Method for controlling defects in gate dielectrics
A method for improving high-.kappa. gate dielectric film (104) properties. The high-.kappa. film (104) is subjected to a two step anneal sequence. The first...
US-7,350,293 Low profile ball-grid array package for high power
A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface...
US-7,350,092 Data synchronization arrangement
A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an...
US-7,349,934 Processor system and method with combined data left and right shift operation
An integrated circuit device (100) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry...
US-7,349,932 High performance FIR filter
A filter includes a tap multiplication circuit and a tap digital-to-analog ("DAC") unit coupled to the tap multiplication circuit. Further, a plurality of clocks...
US-7,349,667 Simplified noise estimation and/or beamforming for wireless communications
A system and method facilitate estimating noise in a received signal. The received signal is formed of a plurality of tones, such as training tones and data...
US-7,349,433 Signaling for parameterized quality of service (QoS) support
The creation, modification, and deletion of a traffic stream 224 with parameterized QoS expectations between two communicating stations 205 and 207, when there...
US-7,349,379 Channel normalization
Soft estimate normalization for weighted multiantenna high-order modulation data channel together with separate antenna pilot channels using averaging in first...
US-7,349,285 Dual port memory unit using a single port memory core
A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock...
US-7,349,237 Plateline driver with RAMP rate control
A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and...
US-7,349,146 System and method for hinge memory mitigation
System and method for reducing failures due to hinge memory in a microdisplay display system. A preferred embodiment includes setting the state of each...
US-7,349,033 Systems and methods for correcting color phase error in video systems
Systems and methods are provided for correcting color phase error in a video decoder system. A demodulator system demodulates the composite input signal and the...
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