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Patent # Description
US-7,279,363 Vertically stacked semiconductor device
A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed...
US-7,279,068 Temperature control assembly for use in etching processes
A temperature control assembly for use in etching processes includes a housing, a cooling conduit, fasteners, and a mounting block. The fasteners couple to the...
US-7,278,078 Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores...
US-7,278,070 Interleaving to avoid wideband interference in a multi-carrier communications system
A multi-carrier communications system with a programmable interleaver and de-interleaver that can change the interleaving rate for data transmitted and received...
US-7,277,920 Implementing applications requiring access to multiple files
The control flow underlying an application is represented in the form of a FSM (Finite State Machine) containing multiple states, transitions between states, and...
US-7,277,828 Methodology for designing high speed receivers below a target bit-error-rate
A method, and associated storage medium containing software and a system, includes extracting a time domain impulse response from parameters that characterize a...
US-7,277,808 Process parameter based I/O timing programmability using electrical fuse elements
Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made...
US-7,277,803 Efficient calculation of a number of transitions and estimation of power dissipation in sequential scan tests
Determining the transition counts at various scan elements of a scan chain (for sequential scan tests) by merely examining the bits of an input vector and the...
US-7,277,537 Tone, modulated tone, and saturated tone detection in a voice activity detection device
In a voice activity detection (VAD) device a method for defining tone signals comprises defining a threshold for zero amplitude change, calculating a zero...
US-7,277,519 Frequency and phase correction in a phase-locked loop (PLL)
In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps...
US-7,277,513 Frequency domain notching with dummy subchannels
System and method for reducing interference to existing devices. A preferred embodiment comprises specifying a frequency range for a set of dummy signals,...
US-7,277,432 Robust indication of MAC level error correction
In digital communications that utilize a data packet format wherein each data packet includes a physical layer (PHY) component and a media access control layer...
US-7,277,308 High performance and low area write precharge technique for CAMs
A technique to pre-charge a CAM block array that includes a plurality of CAM blocks that is organized into at least one rectangular array having rows each having...
US-7,277,263 Local ESD protection for low-capacitance applications
A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power...
US-7,276,958 Charge pump with reduced noise spikes
A voltage supply circuit which suppresses generation of current spikes in the power source current in operation, reduce noise, simplify the circuit ...
US-7,276,888 Precharge circuit for DC/DC boost converter startup
An integrated circuit including a precharge circuit for a DC/DC boost converter which includes a reference current circuit with a MOSFET transistor (MP4) that...
US-7,276,886 Dual buck-boost converter with single inductor
A dual output buck-boost power converter operates with a single inductor to achieve high efficiency with automatic or inherent load balancing. Switches...
US-7,276,408 Reduction of dopant loss in a gate structure
A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively...
US-7,276,401 Adhesion by plasma conditioning of semiconductor chip surfaces
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-7,275,223 Facilitating high-level validation of integrated circuits in parallel with development of blocks in a...
A design management tool which automates the parallel validation of an entire integrated circuit while the individual blocks (together forming the integrated...
US-7,275,078 Distributed web CGI architecture
A distributed web CGI architecture is disclosed. According to one embodiment of the present invention, distributed web common gateway interface architecture...
US-7,274,938 Wired control channel for supporting wireless communication in non-exclusive spectrum
Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum...
US-7,274,916 Differential signal receiver and method
A differential signal receiver and method is disclosed. One embodiment relates to a receiver for receiving a differential signal. The receiver includes a first...
US-7,274,736 Multiple path equalization for multicarrier systems
A dual path equalization structure is used to equalize DMT systems operating over channels in which different impairments dominate the performance of different...
US-7,274,735 Constellation selection in a communication system
A method is provided to provide data to automatically estimate channel performance in a communication system if a different order constellation is used...
US-7,274,732 Echo cancellation in communication systems with asymmetric data rates
A communication device (e.g., a modem) is disclosed as including logic that processes a transmit signal before providing a signal to an echo canceler. The...
US-7,274,716 Multiplexed sigma-delta interface
An improved digital interface circuit that allows a plurality of data streams and other digital information to be output over a single channel. The digital...
US-7,274,581 Array fault testing approach for TCAMs
A novel array fault testing for a TCAM system that includes a plurality of TCAM blocks that is organized into at least one rectangular array having rows each...
US-7,274,545 ESD clamp with "trailing pulse" suppression
In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an...
US-7,274,406 Equilibrium based vertical sync phase lock loop for video decoder
The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync...
US-7,274,347 Prevention of charge accumulation in micromirror devices through bias inversion
Methods and apparatus are provided for preventing charge accumulation in microelectromechanical systems, especially in micromirror array devices having a...
US-7,274,313 High speed data recording with input duty cycle distortion
Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data....
US-7,274,234 Digital storage element architecture comprising integrated multiplexer and reset functionality
A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan...
US-7,274,233 Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality
A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan...
US-7,274,216 Duty cycle controlled CML-CMOS converter
There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving...
US-7,274,046 Tri-gate low power device and method for manufacturing the same
The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first...
US-7,272,750 Expert system for intelligent testing
A computer method for testing a test unit that includes receiving an output of the test unit into a testing system, providing an expert system operably connected...
US-7,272,523 Trimming for accurate reference voltage
A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference...
US-7,272,358 Channelization scheme for wireless local area networks
A four channel wireless network channelization scheme is described that is particularly usable in the ISM frequency band between 2400 MHz and 2483.5 MHz. The...
US-7,272,156 Phased transmit architecture
A Phased Transmit Architecture that allows the embedded processor of an IEEE 802.11e wireless communication device to have a significant number of additional...
US-7,271,748 System and method for providing a thermometer coded output filter
Systems and methods are provided for providing a filtered, thermometer coded output signal from an N bit digital input, where N is an integer greater than one. A...
US-7,271,663 Operational amplifier output stage and method
An operational amplifier includes an input stage for producing a voltage signal in response to an input signal. An output stage includes an output transistor...
US-7,271,494 Adhesion by plasma conditioning of semiconductor chip surfaces
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-7,271,462 Solid-state image sensing device
A solid-state image sensing device that is free of kTC noise, can eliminate black smear and dark current, has a larger numerical aperture, and can eliminate the...
US-7,271,030 Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers...
US-7,269,849 Method and system for access to development environment of another
A highly secure "Design Zones" system is described that promotes collaboration between a manufacturer and owner of compute systems and its partners such as...
US-7,269,848 Method and system for access to development environment of another in a secure zone
A "Design Zones" system provides a highly secure common resource computing environment or design zone with services on the common resource or design zone being...
US-7,269,769 AC propagation testing preventing sampling test data at Capture-DR state
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-7,269,707 Multiple patches to on-chip ROM in a processor with a multilevel memory system without affecting performance
A programmable address decoder is common to the on-chip ROM and on-chip RAM. The programmable address decoder conditionally routes accesses to portions of the...
US-7,269,670 Analog ethernet detector having first logic circuit and second logic circuit coupled to output signal detectors...
An analog Ethernet detector determines if an IEEE 1394b long haul application using Category 5 (CAT 5 UTP) cable, is connected to an Ethernet which share certain...
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