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Patent # Description
US-7,286,019 Method and system for amplifying a signal
According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that...
US-7,285,830 Lateral bipolar junction transistor in CMOS flow
An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are...
US-7,284,212 Minimizing computational complexity in cell-level noise characterization
Reducing the number of computations required to pre-characterize cells in a cell-library. In an embodiment, a worst case vector which propagates most noise on an...
US-7,284,170 JTAG circuit transferring data between devices on TMS terminals
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication...
US-7,284,143 System and method for reducing clock skew
In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input...
US-7,284,142 Real time interrupt module for operating systems and time triggered applications
An interrupt timer module comprises a prescale counter (PSC) incremented by a real-time interrupt clock signal (RTICLK), a prescale compare value register (CVR)...
US-7,284,139 Processor having real-time power conservation
A processor, comprising a monitor for, depending on the respective embodiment, measuring a relative amount of idle time, activity time, or idle time and activity...
US-7,283,618 Automatic line pair detection in a modem
The present invention provides a solution that automatically detects and connects the properly terminated line pair and then allows modem training to proceed....
US-7,283,590 Signal processing approach for channel coding based on inter-symbol-interference insertion
An inter-symbol-interference (ISI) coder with mapper and linear filter and a technique of channel encoding deliberately inserts inter-symbol-interference (ISI)...
US-7,283,554 Network manager for a hybrid network environment
A system, apparatus and method are disclosed for implementing a managed network in a hybrid network environment to support nodes having managed network...
US-7,283,343 Integrated reverse battery protection circuit for an external MOSFET switch
A reverse battery protection circuits that provides an integrated reverse battery condition solution for protection of external NMOS switches during the reverse...
US-7,283,157 Automatic level control (ALC) for video signals
Disclosed are methods and systems for automatic level control (ALC) in a video signal processing system. The new ALC of the invention takes into account the gain...
US-7,283,082 High-speed, high-resolution voltage output digital-to-analog converter and method
A string DAC having 2.sup.M string resistors includes a plurality of switches for selectively coupling, according to the decoding of an M-bit MSB subword, the...
US-7,282,964 Circuit for detecting transitions on either of two signal lines referenced at different power supply levels
A transition detect circuit includes: a first input port referenced to a first supply voltage node and a second input port referenced to a second supply voltage...
US-7,282,905 System and method for IDDQ measurement in system on a chip (SOC) design
System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for...
US-7,282,895 Active dropout optimization for current mode LDOs
A DC/DC converter has a linear voltage regulator for reducing or eliminating the output ripple of the converter with a minimum loss of efficiency. The converter...
US-7,282,767 Guardwall structures for ESD protection
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to...
US-7,282,436 Plasma treatment for silicon-based dielectrics
An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor...
US-7,282,393 Microelectromechanical device packages with integral heaters
A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The...
US-7,281,223 System and method for modeling an integrated circuit system
The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a...
US-7,281,183 Data retaining boundary scan cell
Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one...
US-7,281,009 VLSI architecture and implementation for single cycle insertion of multiple records into a priority sorted list
A data processing apparatus simultaneously sorts n input data words into a sorted list of m list entries. The apparatus includes a pre-sorting network sorting...
US-7,280,622 Low-complexity hierarchical decoding for communications systems using multidimensional QAM signaling
A reduced search space minimum distance decoding method provides average probability of error performance close to optimal MAP decoding. The decoding algorithm...
US-7,280,585 Parallel interference cancellation device for multi-user CDMA systems
This invention provide parallel interference cancellation for wireless communication base stations. Received user inputs symbols are spread by means of...
US-7,280,330 ESD protection for RF power amplifier circuits
An electrostatic discharge (ESD) device for protecting a power amplifier circuit is disclosed. The ESD device comprises a first ESD protection circuit coupled...
US-7,280,250 Method and apparatus for rendering large patterns in a small memory printer
A method of performing a pattern fill operation of a pattern into a clipping region divides dividing the pattern into a plurality of bands. For each band the...
US-7,280,126 Methods and apparatus for converting an orthogonal pixel format to a diamond pixel format
Apparatus for converting orthogonal data to a format suitable for displaying the image on a diamond-shaped pixel array. A stream of digital data formatted for...
US-7,280,116 Pixel data preprocessing methods and systems
Methods and systems are disclosed for preprocessing video display pixel data. A preprocessor is provided with a selectable gamma correction mode and a selectable...
US-7,279,974 Fully differential large swing variable gain amplifier
The fully differential large swing variable gain amplifier circuit includes: a first 5-transistor transconductor having a common mode node; and a second...
US-7,279,966 Systems for pseudo-BD modulation
An amplifier system in accordance with an aspect of the present invention comprises a switching amplifier that drives a load with a pulse-width modulated (PWM)...
US-7,279,920 Expeditious and low cost testing of RFID ICs
System and method for integrated circuit manufacturing. A preferred embodiment comprises transmitting a first set of data to integrated circuits (ICs) while they...
US-7,279,738 Semiconductor device with an analog capacitor
A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the...
US-7,279,406 Tailoring channel strain profile by recessed material composition control
The present invention facilitates semiconductor fabrication by providing methods of fabrication that tailor applied strain profiles to channel regions of...
US-7,279,397 Shallow trench isolation method
A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions...
US-7,279,363 Vertically stacked semiconductor device
A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed...
US-7,279,068 Temperature control assembly for use in etching processes
A temperature control assembly for use in etching processes includes a housing, a cooling conduit, fasteners, and a mounting block. The fasteners couple to the...
US-7,278,078 Built-in self-test arrangement for integrated circuit memory devices
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores...
US-7,278,070 Interleaving to avoid wideband interference in a multi-carrier communications system
A multi-carrier communications system with a programmable interleaver and de-interleaver that can change the interleaving rate for data transmitted and received...
US-7,277,920 Implementing applications requiring access to multiple files
The control flow underlying an application is represented in the form of a FSM (Finite State Machine) containing multiple states, transitions between states, and...
US-7,277,828 Methodology for designing high speed receivers below a target bit-error-rate
A method, and associated storage medium containing software and a system, includes extracting a time domain impulse response from parameters that characterize a...
US-7,277,808 Process parameter based I/O timing programmability using electrical fuse elements
Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made...
US-7,277,803 Efficient calculation of a number of transitions and estimation of power dissipation in sequential scan tests
Determining the transition counts at various scan elements of a scan chain (for sequential scan tests) by merely examining the bits of an input vector and the...
US-7,277,537 Tone, modulated tone, and saturated tone detection in a voice activity detection device
In a voice activity detection (VAD) device a method for defining tone signals comprises defining a threshold for zero amplitude change, calculating a zero...
US-7,277,519 Frequency and phase correction in a phase-locked loop (PLL)
In one embodiment, a system for frequency and phase correction in a phase-locked loop (PLL) includes a phase frequency detector, first and second charge pumps...
US-7,277,513 Frequency domain notching with dummy subchannels
System and method for reducing interference to existing devices. A preferred embodiment comprises specifying a frequency range for a set of dummy signals,...
US-7,277,432 Robust indication of MAC level error correction
In digital communications that utilize a data packet format wherein each data packet includes a physical layer (PHY) component and a media access control layer...
US-7,277,308 High performance and low area write precharge technique for CAMs
A technique to pre-charge a CAM block array that includes a plurality of CAM blocks that is organized into at least one rectangular array having rows each having...
US-7,277,263 Local ESD protection for low-capacitance applications
A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power...
US-7,276,958 Charge pump with reduced noise spikes
A voltage supply circuit which suppresses generation of current spikes in the power source current in operation, reduce noise, simplify the circuit ...
US-7,276,888 Precharge circuit for DC/DC boost converter startup
An integrated circuit including a precharge circuit for a DC/DC boost converter which includes a reference current circuit with a MOSFET transistor (MP4) that...
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