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Patent # Description
US-7,348,855 Bias circuitry for cascode transistor circuit
An integrated circuit includes a composite transistor including at least a first transistor of a first technology type having a first group of intrinsic...
US-7,348,812 Multiphased triangular wave oscillating circuit and switching regulator using it
To oscillate and output multiphased triangular waves with a designed waveform shape, wave crest value, and phase relationship. This multiphased triangular wave...
US-7,348,797 Functional cells for automated I/O timing characterization of an integrated circuit
Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive...
US-7,348,643 Semiconductor dual guardring arrangement
A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions....
US-7,348,265 Semiconductor device having a silicided gate electrode and method of manufacture therefor
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The...
US-7,348,232 Highly activated carbon selective epitaxial process for CMOS
In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a...
US-7,348,228 Deep buried channel junction field effect transistor (DBCJFET)
A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed....
US-7,346,898 Method for scheduling processors and coprocessors with bit-masking
Multiple coprocessor scheduling of parallel processing steps control with bit arithmetic using a bitmask for each data block buffer indicating next processing...
US-7,346,821 IC with JTAG port, linking module, and off-chip TAP interface
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP...
US-7,346,731 High performance and scalable width expansion architecture for fully parallel CAMs
A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example...
US-7,346,121 Code division multiple access wireless system with closed loop mode using ninety degree phase rotation and...
A wireless communication system (10). The system comprises a user station (12). The user station comprises despreading circuitry (22) for receiving and...
US-7,346,113 Method and circuit for stop of signals quantized using noise-shaping
A system and method are provided for stopping a quantized signal from a noise-shaper with a significantly reduced inband transient, compared to a traditional...
US-7,346,100 Estimating gain and phase imbalance in upconverting transmitters
Estimation of gain and phase imbalance of an upconverting transmitter. A transmitter transmits symbols containing vector components of pre-specific relationship...
US-7,346,026 4X design for wireless local area network throughput enhancement
A system and method for wireless local area network throughput enhancement includes an access point and an endpoint station in a wireless computer network...
US-7,346,005 Adaptive playout of digital packet audio with packet format independent jitter removal
In order to reduce distortion in playout of audio received in a packet over a packet network, the playout unit needs to determine the relative delay of adjacent...
US-7,346,003 Method of increasing noise immunity with a simulated preamble
Circuitry and method for receiving and decoding a data stream without a preamble transmitted from the transmitting device. The invention includes circuitry in...
US-7,345,807 Laminated package
A system and method of aligning a micromirror array to the micromirror package and the micromirror package to a display system. One embodiment provides a method...
US-7,345,806 Method and apparatus for characterizing microelectromechanical devices on wafers
The invention provides a method and apparatus for evaluating the quality of microelectromechanical devices having deformable and deflectable members using...
US-7,345,782 Efficient implementation of raster operations flow
According to one aspect, a printer supports transparency operations by generating mask data at interpretation stage which indicates whether each bit of a page...
US-7,345,601 Variable length coding algorithm for multiple coding modes
A novel algorithm is shown that allows efficient generation of Variable Length Codes using a Very Large Instruction Word processor with multiple execution units....
US-7,345,600 Asynchronous sampling rate converter
Asynchronous sampling rate converter with input/output frequency ratio estimation and polyphase filtering uses FIFO level feedback to adaptively control...
US-7,345,573 Integration of thin film resistors having different TCRs into single die
An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a...
US-7,345,542 Circuit and method for avoiding circuit performance degradation caused by time-variable thermal imbalances
A signal processing circuit includes a circuit stage for operating on signals in a signal path of an input signal, including main circuitry for operating on...
US-7,345,529 Chopper stabilized amplifier without DC output ripple
The chopper stabilized amplifier circuit includes: an amplifier; a first current mirror coupled to an output of the amplifier through a first switch; a second...
US-7,345,528 Method and apparatus for improved clock preamplifier with low jitter
A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising...
US-7,345,518 Digital storage element with dual behavior
A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a...
US-7,345,355 Complementary junction-narrowing implants for ultra-shallow junctions
Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include...
US-7,345,343 Integrated circuit having a top side wafer contact and a method of manufacture therefor
The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without...
US-7,345,001 Gate dielectric having a flat nitrogen profile and method of manufacture therefor
The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated...
US-7,344,987 Method for CMP with variable down-force adjustment
The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed....
US-7,344,985 Nickel alloy silicide including indium and a method of manufacture therefor
The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The...
US-7,344,957 SOI wafer with cooling channels and a method of manufacture thereof
A method (100) of forming a silicon-on-insulator (SOI) wafer includes forming one or more channels in a top surface of a first wafer (104), and forming an...
US-7,344,951 Surface preparation method for selective and non-selective epitaxial growth
According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having...
US-7,344,947 Methods of performance improvement of HVMOS devices
Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second...
US-7,344,939 Ferroelectric capacitor with parallel resistance for ferroelectric memory
Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge...
US-7,344,929 Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity
The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for...
US-7,344,916 Package for a semiconductor device
A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond...
US-7,344,900 Laser scribe on front side of semiconductor wafer
Disclosed are a semiconductor wafer (10) having a front side laser scribe (22) and the methods for manufacturing the same. The methods of the invention include...
US-7,343,591 Real-time data exchange on demand
A real time data exchange on demand system for transferring real time data between a host processor and a target processor is described. The target processor...
US-7,343,537 IC with protocol selection memory coupled to serial scan path
A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register...
US-7,343,045 Image information compression device
This invention controls the code generation quantity adaptively with respect to the pattern of images and changes in the images, etc., so as to alleviate...
US-7,343,019 Streaming normalization
A normalization for streaming digital audio signals applies a gain factor according to the maximum sample magnitude in a window of samples and compare the gain...
US-7,342,962 Transcoders and methods
Transcoding as from MPEG-2 SDTV to MPEG-4 CIF reuses motion vectors and downsamples in the frequency (DCT) domain with differing treatments of frame-DCT and...
US-7,342,937 Spectrally flexible band plans with reduced filtering requirements
The present invention provides, in one embodiment, a method of simplifying filtering with respect to a band plan. The method includes selecting a reflection...
US-7,342,450 Slew rate enhancement circuitry for folded cascode amplifier
A folded-cascode operational amplifier including a differential input stage (19) and a class AB output stage (20) includes a first slew boost current mirror (13)...
US-7,342,447 Systems and methods for driving an output transistor
A system and method is provided for driving an output transistor. The system and method employ a sense control to adjust a drive strength associated with driving...
US-7,342,315 Method to increase mechanical fracture robustness of porous low k dielectric materials
The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a...
US-7,341,941 Methods to facilitate etch uniformity and selectivity
A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect...
US-7,341,933 Method for manufacturing a silicided gate electrode using a buffer layer
The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for...
US-7,341,808 Method and system for contiguous proximity correction for semiconductor masks
According to one embodiment, a method for patterning a set of features for a semiconductor device includes providing a mask including a substrate and at least...
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