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Patent # Description
US-7,276,401 Adhesion by plasma conditioning of semiconductor chip surfaces
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-7,275,223 Facilitating high-level validation of integrated circuits in parallel with development of blocks in a...
A design management tool which automates the parallel validation of an entire integrated circuit while the individual blocks (together forming the integrated...
US-7,275,078 Distributed web CGI architecture
A distributed web CGI architecture is disclosed. According to one embodiment of the present invention, distributed web common gateway interface architecture...
US-7,274,938 Wired control channel for supporting wireless communication in non-exclusive spectrum
Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum...
US-7,274,916 Differential signal receiver and method
A differential signal receiver and method is disclosed. One embodiment relates to a receiver for receiving a differential signal. The receiver includes a first...
US-7,274,736 Multiple path equalization for multicarrier systems
A dual path equalization structure is used to equalize DMT systems operating over channels in which different impairments dominate the performance of different...
US-7,274,735 Constellation selection in a communication system
A method is provided to provide data to automatically estimate channel performance in a communication system if a different order constellation is used...
US-7,274,732 Echo cancellation in communication systems with asymmetric data rates
A communication device (e.g., a modem) is disclosed as including logic that processes a transmit signal before providing a signal to an echo canceler. The...
US-7,274,716 Multiplexed sigma-delta interface
An improved digital interface circuit that allows a plurality of data streams and other digital information to be output over a single channel. The digital...
US-7,274,581 Array fault testing approach for TCAMs
A novel array fault testing for a TCAM system that includes a plurality of TCAM blocks that is organized into at least one rectangular array having rows each...
US-7,274,545 ESD clamp with "trailing pulse" suppression
In a method and system for protecting a semiconductor device from an electrostatic discharge (ESD) event, an ESD tester generates an ESD event by providing an...
US-7,274,406 Equilibrium based vertical sync phase lock loop for video decoder
The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync...
US-7,274,347 Prevention of charge accumulation in micromirror devices through bias inversion
Methods and apparatus are provided for preventing charge accumulation in microelectromechanical systems, especially in micromirror array devices having a...
US-7,274,313 High speed data recording with input duty cycle distortion
Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data....
US-7,274,234 Digital storage element architecture comprising integrated multiplexer and reset functionality
A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan...
US-7,274,233 Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality
A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan...
US-7,274,216 Duty cycle controlled CML-CMOS converter
There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving...
US-7,274,046 Tri-gate low power device and method for manufacturing the same
The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first...
US-7,272,750 Expert system for intelligent testing
A computer method for testing a test unit that includes receiving an output of the test unit into a testing system, providing an expert system operably connected...
US-7,272,523 Trimming for accurate reference voltage
A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference...
US-7,272,358 Channelization scheme for wireless local area networks
A four channel wireless network channelization scheme is described that is particularly usable in the ISM frequency band between 2400 MHz and 2483.5 MHz. The...
US-7,272,156 Phased transmit architecture
A Phased Transmit Architecture that allows the embedded processor of an IEEE 802.11e wireless communication device to have a significant number of additional...
US-7,271,748 System and method for providing a thermometer coded output filter
Systems and methods are provided for providing a filtered, thermometer coded output signal from an N bit digital input, where N is an integer greater than one. A...
US-7,271,663 Operational amplifier output stage and method
An operational amplifier includes an input stage for producing a voltage signal in response to an input signal. An output stage includes an output transistor...
US-7,271,494 Adhesion by plasma conditioning of semiconductor chip surfaces
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-7,271,462 Solid-state image sensing device
A solid-state image sensing device that is free of kTC noise, can eliminate black smear and dark current, has a larger numerical aperture, and can eliminate the...
US-7,271,030 Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers...
US-7,269,849 Method and system for access to development environment of another
A highly secure "Design Zones" system is described that promotes collaboration between a manufacturer and owner of compute systems and its partners such as...
US-7,269,848 Method and system for access to development environment of another in a secure zone
A "Design Zones" system provides a highly secure common resource computing environment or design zone with services on the common resource or design zone being...
US-7,269,769 AC propagation testing preventing sampling test data at Capture-DR state
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-7,269,707 Multiple patches to on-chip ROM in a processor with a multilevel memory system without affecting performance
A programmable address decoder is common to the on-chip ROM and on-chip RAM. The programmable address decoder conditionally routes accesses to portions of the...
US-7,269,670 Analog ethernet detector having first logic circuit and second logic circuit coupled to output signal detectors...
An analog Ethernet detector determines if an IEEE 1394b long haul application using Category 5 (CAT 5 UTP) cable, is connected to an Ethernet which share certain...
US-7,269,558 Decoding multiple HMM sets using a single sentence grammar
For a given sentence grammar, speech recognizers are often required to decode M sets of HMMs each of which models a specific acoustic environment. In order to...
US-7,269,528 Method evaluating threshold level of a data cell in a memory device
A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal...
US-7,269,175 AAL2 transmitter for voice-packed and signaling management-packed interleaving on an ATM connection
The present invention provides an apparatus, system and method for transmitting asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL)...
US-7,268,934 Micromirror and post arrangements on substrates
A micromirror of a micromirror array of a spatial light modulator used in display systems comprises a mirror plate attached to a hinge that is supported by two...
US-7,268,837 Method and system for automated convergence and focus verification of projected images
A method and system that objectively measures the convergence and focus of a 2 or 3 spatial light modulator (SLM) projection display. The system uses five (5)...
US-7,268,571 Method for validating and monitoring automatic test equipment contactor
A method and apparatus is provided for characterizing a contactor for automated semiconductor device testing, the method first comprising placing the contactor...
US-7,268,561 USB attach detection for USB 1.1 and USB OTG devices
An apparatus for detection of a USB host or a USB OTG device being attached to Vbus connector terminal of a USB device includes an attach detection pull down...
US-7,268,415 Semiconductor device having post-mold nickel/palladium/gold plated leads
A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of...
US-7,268,399 Enhanced PMOS via transverse stress
In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of...
US-7,268,394 JFET structure for integrated circuit and fabrication method
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in...
US-7,268,088 Formation of low leakage thermally assisted radical nitrided dielectrics
One or more aspects of the present invention relate to forming a dielectric suitable for use as a gate dielectric in a transistor. The gate dielectric is formed...
US-7,268,073 Post-polish treatment for inhibiting copper corrosion
Methods (102) are presented for protecting copper structures (26) from corrosion in the fabrication of semiconductor devices (2), wherein a thin semiconductor or...
US-7,268,045 N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects
An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions,...
US-7,267,861 Solder joints for copper metallization having reduced interfacial voids
A metal interconnect structure (100) comprising a bond pad (101), which has copper with at least 70 volume percent composed of crystal grains expanding more than...
US-7,267,726 Method and apparatus for removing polymer residue from semiconductor wafer edge and back side
A method for cleaning a semiconductor device has the steps of securing a wafer (16) with a modified chuck (11) and applying a cleaning solution (18) to the...
US-7,266,824 Address space priority arbitration
A digital system and method of operation is provided in which several processors (400[]) are connected to a shared resource (432). Each processor has a...
US-7,266,619 Framework for high-performance hardware abstraction
In some embodiments, a system comprises a processor that executes an algorithm. Coupled to the processor is memory that stores the algorithm. In addition, the...
US-7,265,926 High speed hard disk drive with symmetric writer
A disk drive data storage system, comprising a magnetic disk a head for writing data to the disk, and circuitry for providing a first voltage (HWX) to a first...
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