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Patent # Description
US-7,319,701 Modem relay protocol redundancy for reliable low speed modem communications over IP networks with substantial...
Minimized Wave-zone Buoyancy is a new approach to oil and gas platform design with superior construction and performance characteristics compared to state-of-art...
US-7,319,419 Switched capacitor circuit with current source offset DAC and method
A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational...
US-7,319,357 System for controlling switch transistor performance
The present invention provides a system for controlling performance of a switch transistor (106)--one that is implemented within a circuitry segment (100) to...
US-7,319,354 Signal processing apparatus having internal clock signal source
A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock...
US-7,319,275 Adhesion by plasma conditioning of semiconductor chip
A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated...
US-7,318,208 Method for circuit sensitivity driven parasitic extraction
The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at...
US-7,318,176 Tracing program counter addresses using native program counter format and instruction count format
A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter...
US-7,318,112 Universal interface simulating multiple interface protocols
A universal interface interfaces between a variety of different data processing devices by the generation, storage, proper routing, and timed output of data...
US-7,318,017 Collecting and exporting on-chip data processor trace and timing information with differing collection and...
Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is...
US-7,317,776 Efficient pseudo-noise sequence generation for spread spectrum applications
The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used,...
US-7,317,760 System and method for finger and path management in receivers
System and method for managing finger and path resources. A preferred embodiment comprises receiving a delay profile, processing paths from the delay profile,...
US-7,317,355 Over-current detection for a power field-effect transistor (FET)
A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection...
US-7,315,992 Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation...
US-7,315,971 Systems and methods for improved memory scan testability
A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the...
US-7,315,905 Software controlled hard reset of mastering IPS
A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a...
US-7,315,879 Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and...
A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate...
US-7,315,808 Correlating on-chip data processor trace information for export
In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a...
US-7,315,806 Enhanced negative constraint calculation for event driven simulations
A technique to enable accurate timing and functional verification in a negative constraint calculation (NCC) implemented event-driven logic simulators when there...
US-7,315,601 Low-noise sigma-delta frequency synthesizer
A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding...
US-7,315,596 Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability
The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to...
US-7,315,573 Channel monitoring for improved parameter selection in a communication system
A method is provided for automatically improving throughput of an active channel in a communication system comprising: receiving input from one or more modules...
US-7,315,540 Random access memory based space time switch architecture
A data switching circuit (10). The data switching circuit comprises at least one input (10.sub.in) for receiving during a same time period a plurality of data...
US-7,315,294 Deinterleaving transpose circuits in digital display systems
The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the...
US-7,315,261 Method for converting data from pixel format to bitplane format
This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform...
US-7,315,191 Digital storage element architecture comprising dual scan clocks and reset functionality
A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and...
US-7,315,183 Single-supply voltage translator input having low supply current
A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a...
US-7,315,182 Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode...
A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential...
US-7,314,816 Masking layer in substrate cavity
A package that resists creation of particles in a package cavity. A package according to one embodiment of the present invention contains a mechanical device...
US-7,314,800 Application of different isolation schemes for logic and embedded memory
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and...
US-7,313,705 Implementation of a secure computing environment by using a secure bootloader, shadow memory, and protected memory
A computer system with a secure bootloading function is disclosed. Security logic (20) is implemented on-chip with a central processing unit (CPU) (10), and...
US-7,313,501 Method and system for determining the location of a potential defect in a device based on a temperature profile
According to one embodiment of the invention a method for determining the location of a potential defect in a device includes scanning a surface of the device...
US-7,313,490 Wavelet analysis of one or more time domain reflectometry (TDR) signals to determine one or more...
In one embodiment, a method for wavelet analysis of one or more time domain reflectometry (TDR) signals to determine one or more characteristics of one or more...
US-7,313,190 Efficient bit interleaver for a multi-band OFDM ultra-wideband system
An efficient bit interleaving scheme for a multi-band OFDM ultra-wideband (UWB) system. The encoded bits of the multi-band OFDM system are interleaved within...
US-7,313,130 Spectrally compatible mask for enhanced upstream data rates in DSL systems
A method and apparatus for providing extended upstream data transmission in a band having a lowest frequency f.sub.0 by an end user terminal unit in an...
US-7,312,915 Microelectromechanical devices with low inertia movable elements
A microelectromechanical device having a movable element with low mass inertia is disclosed herein. The movable element is held on a substrate such that the...
US-7,312,738 Apparatus and method for sigma delta signal treatment
A sigma delta signal treating apparatus includes: (a) a low pass filtered signal path including at least one low pass filter; and (b) a quantization noise...
US-7,312,736 Trading off visibility for volume of data when profiling memory events
When tracing memory events the required bandwidth may be reduced by forming a logical OR of several memory event signals to determine the location of memory...
US-7,312,481 Reliable high-voltage junction field effect transistor and method of manufacture therefor
The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One...
US-7,312,151 System for ultraviolet atmospheric seed layer remediation
The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate...
US-7,312,119 Stacked capacitor and method of fabricating same
The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a...
US-7,310,756 JTAG state machines with respective enable input and select input
A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
US-7,310,749 Apparatus and method for trace stream identification of a processor debug halt signal
When a DEBUG HALT signal is generated in a target processor during a test procedure, a debug halt sync marker is generated in a program counter trace stream. The...
US-7,310,365 Group decision rule in code tracking using a delay lock loop (DLL)
System and method for code acquisition in a wireless communications system with a delay lock loop. A preferred embodiment comprises assigning a delay lock loop...
US-7,310,058 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)
A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which...
US-7,310,016 Chopper-stabilized operational amplifier and method
An amplifier circuit includes an input chopping circuit for chopping first and second input signals, a transconductance stage for amplifying an output of the...
US-7,309,909 Leadframes for improved moisture reliability of semiconductor devices
A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of...
US-7,309,651 Method for improving reliability of copper interconnects
Doping copper interconnects (100) with silicon (115) has been shown to improve Electromigration and Via Stress Migration reliability. After copper (118) is...
US-7,309,648 Low profile, chip-scale package and method of fabrication
Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a...
US-7,308,629 Addressable tap domain selection circuit with TDI/TDO external terminal
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial...
US-7,307,907 SRAM device and a method of operating the same to reduce leakage current during a sleep mode
An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a...
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