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| Patent # | Description |
|---|---|
| US-7,583,156 |
Oscillator with multi-tap inductor, capacitors, and negative-Gm stages System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. An electronic communications device includes a controller to... |
| US-7,583,147 |
Buffer drive The present invention relates to a CMOS buffer circuit for liquid crystal display (LCD) drivers, which includes a single stage operational transconductance... |
| US-7,583,133 |
Self-oscillating regulated low-ripple charge pump and method Charge pump circuitry (30) compares bottom plate voltages of first (C1) and second (C2) flying capacitors in a current mode charge pump (1B) to a reference value... |
| US-7,582,963 |
Vertically integrated system-in-a-package According to one embodiment of the invention, a method of forming a system-in-a-package includes providing a first substrate, coupling a first die to a top... |
| US-7,582,521 |
Dual metal gates for mugfet device Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the... |
| US-7,581,159 |
Simplified decoding using structured and punctured LDPC codes A communications transceiver for transmitting and receiving coded communications, with the coding corresponding to a low-density parity check code, is disclosed.... |
| US-7,581,139 |
Distinguishing between two classes of trace information A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time... |
| US-7,581,082 |
Software source transfer selects instruction word sizes This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and... |
| US-7,581,049 |
Bus controller A single bus apparatus enables the simultaneous execution of both high-speed data transfer, which requires real time operation, and low-speed data transfer. At... |
| US-7,580,968 |
Processor with scaled sum-of-product instructions A method of performing a scaled sum-of-product operation in a processor in response to multiply-and-accumulate (MAC) instructions. The method includes accessing... |
| US-7,580,967 |
Processor with maximum and minimum instructions A method of operating a processor in a variable bit-length environment by performing a maximum limit function and minimum limit function. The method comprises... |
| US-7,580,965 |
Discrete-time convolution cycle reduction with programmable digital signal
processor A programming algorithm reduces from .theta. (2N.sup.2) to .theta. (N.sup.2) the number of multiply-and-accumulate (MAC) instructions required to perform a... |
| US-7,580,807 |
Test protocol manager for massive multi-site test Disclosed herein is a massive multi-site (MMS) testing architecture. The MMS architecture includes a MMS interface on each of a plurality of devices under test.... |
| US-7,580,768 |
Method of adjusting process variables in a processing flow A method of adjusting process variables in a processing flow is disclosed. Processed samples are tested to determine sample parameters of the tested samples. The... |
| US-7,580,761 |
Fixed-size cross-correlation computation method for audio time scale
modification A time-domain time-scale modification method based on the synchronous overlap-and-add method consists of a generalization of the envelope-matching time-scale... |
| US-7,580,492 |
Clock recovery Clock recovery apparatus having an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein the early/late voter... |
| US-7,579,975 |
DAC architecture for an ADC pipeline A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one... |
| US-7,579,858 |
Semiconductor device and inspection method thereof A semiconductor device is disclosed. The device has a photodiode isolated by element isolating regions (Ia, 14a, 14b) characterized by the following facts: on... |
| US-7,579,541 |
Automatic page sequencing and other feedback action based on analysis of
audio performance data Speech or musical performance is electronically analyzed using DSP techniques and is compared to a stored text script or musical score, to enable display of and... |
| US-7,578,422 |
Bond capillary design for ribbon wire bonding A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an... |
| US-7,577,981 |
Updating embedded firmware in a video system An electronic device (18). The device comprises an analog (16) interface for receiving an analog waveform. The device also comprises an image screen (20) and... |
| US-7,577,774 |
Independent source read and destination write enhanced DMA The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and... |
| US-7,577,565 |
Adaptive voice playout in VOP Packetized CELP-encoded speech playout with frame truncation during silence and frame expansion method dependent upon voicing classification with voiced frame... |
| US-7,577,248 |
Method and apparatus for echo cancellation, digit filter adaptation,
automatic gain control and echo... Hands-free phones with voice activity detection using a comparison of frame power estimate with an adaptive frame noise power estimate, automatic gain control... |
| US-7,576,902 |
Spatial light modulator mirror metal having enhanced reflectivity In accordance with the teachings of the present invention, a spatial light modulator mirror metal having enhanced reflectivity is provided. In a particular... |
| US-7,576,797 |
Automatic white balancing via illuminant scoring autoexposure by neural
network mapping Automatic white balancing and/or autoexposure as useful in a digital camera extracts color channel gains from comparisons of image colors with reference colors... |
| US-7,576,759 |
Parallel dithering contour mitigation A method of producing an image. Image data word comprising image data bits for a portion of the image is received at a first frame rate. At least two threshold... |
| US-7,576,758 |
Using super-pixels for efficient in-place rotation of images Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at... |
| US-7,576,668 |
Reducing the time to convert an analog input sample to a digital code in
an analog to digital converter (ADC) A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which... |
| US-7,576,595 |
Buffer circuit The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power... |
| US-7,576,594 |
Method and device for reducing influence of early effect A method is provided for improving the performance of a circuit containing a three-terminal device. In the operation of a circuit containing three-terminal... |
| US-7,576,568 |
Self-selecting precharged domino logic circuit A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the... |
| US-7,575,969 |
Buried layer and method A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep... |
| US-7,575,147 |
Compliant wirebond pedestal A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906).... |
| US-7,574,641 |
Probeless testing of pad buffers on wafer The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die. |
| US-7,574,586 |
Efficient transfer of branch information A system comprising a processor adapted to execute software code comprising branch instructions and a trace logic coupled to the processor and adapted to... |
| US-7,574,584 |
Splitting execution of a floating-point add instruction between an integer
pipeline for performing mantissa... In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and... |
| US-7,574,351 |
Arranging CELP information of one frame in a second packet Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate... |
| US-7,574,278 |
Scheduling system and method A method and apparatus for scheduling in a wafer fab. The method comprising means for weighting inventories according to at least one of logpoints or reticle,... |
| US-7,574,181 |
System and method for preprocessing a signal for transmission by a power
amplifier System and method for preprocessing a signal for transmission by a power amplifier. In a preferred embodiment a multiple input multiple output processor is... |
| US-7,573,960 |
Narrow band interference cancellation technique for OFDM transmitters A computational algorithm provides new and effective interference cancellation of the in-band spurious signals for the Orthogonal Frequency Division Multiplex... |
| US-7,573,884 |
Cable modem downstream channel bonding re-sequencing mechanism A novel apparatus and method of packet re-sequencing applicable to systems wherein packets are assigned sequence numbers and transmitted over multiple channels... |
| US-7,573,830 |
Integrated programmable device for safety critical applications An integrated programmable device has a plurality of signal inputs (P1, P2, P3) connected to respective ones of a plurality of switching elements (S1, S2, S3).... |
| US-7,573,414 |
Maintaining a reference voltage constant against load variations A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at... |
| US-7,573,405 |
System updating accumulated statistics coding variable values after
multiple encodings A system for, and method of, entropy coding. In one embodiment, the system includes: (1) a memory configured to contained initialized accumulated statistics... |
| US-7,573,325 |
CMOS reference current source A CMOS reference current source comprises two circuit branches connected in parallel between supply terminals. The first circuit branch includes a series... |
| US-7,573,307 |
Systems and methods for reduced area delay locked loop Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area... |
| US-7,573,139 |
Packed system of semiconductor chips having a semiconductor interposer A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the... |
| US-7,573,137 |
Controlling flip-chip techniques for concurrent ball bonds in
semiconductor devices A device has a first semiconductor chip (101) with contact pads in an interior first set (102) and a peripheral second set (103). A deformed sphere (104) of... |
| US-7,573,111 |
Methods for depositing, releasing and packaging micro-electromechanical
devices on wafer substrates A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from... |
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