Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: texas instruments
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,466,476 |
Sloped cantilever beam electrode for a MEMS device A method of tilting a micromirror includes providing a substrate, a sloped electrode outwardly from the substrate, and a sloped electrode positioning system... |
| US-7,466,402 |
System and method for testing a lighting diode A system for testing a lighting diode includes one or more nozzles, a probe, and a detector, where the lighting diode is operable to emit light in response to a... |
| US-7,466,259 |
Methods and apparatus to measure a voltage on an integrated circuit Methods and apparatus to measure a voltage on an integrated circuit are disclosed. An example method to measure a voltage on an integrated circuit provides a... |
| US-7,466,207 |
Gain calibration of a digital controlled oscillator A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO)... |
| US-7,466,201 |
Class AB output stage and method for providing wide supply voltage range A class AB output stage includes first (M.sub.P) and a second (M.sub.N) output transistors having sources coupled to first (V.sub.DD) and second reference... |
| US-7,466,115 |
Soft-start circuit and method for power-up of an amplifier circuit A method and circuit for providing a soft start-up process for an amplifier circuit to reduce or prevent destructive overshoot of an output voltage are provided.... |
| US-7,466,018 |
MEMS device wafer-level package A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of... |
| US-7,466,009 |
Method for reducing dislocation threading using a suppression implant The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device... |
| US-7,465,635 |
Method for manufacturing a gate sidewall spacer using an energy beam
treatment The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may... |
| US-7,464,361 |
System and method for asynchronous logic synthesis from high-level
synchronous descriptions A method for generating an equivalent asynchronous handshake circuit from a synchronous description of its intended behavior. |
| US-7,464,347 |
Method for collaboration of issue-resolution by different projects in a
processor design This invention is a toolset upgrading the basic WEBS system update that facilitates tracking design bugs. This invention provides an effective means for... |
| US-7,464,283 |
System and method for producing precision timing signals by controlling
register banks to provide a phase... Systems and methods are provided for providing precision timing signals. A first register bank, driven by a first clock signal, provides a first delay along a... |
| US-7,464,033 |
Decoding multiple HMM sets using a single sentence grammar For a given sentence grammar, speech recognizers are often required to decode M sets of HMMs each of which models a specific acoustic environment. In order to... |
| US-7,464,018 |
Stalling CPU pipeline to prevent corruption in trace while maintaining
coherency with asynchronous events A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out... |
| US-7,463,873 |
Wireless communications device having type-II all-digital phase-locked
loop (PLL) System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a... |
| US-7,463,869 |
Low noise high isolation transmit buffer gain control mechanism A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an... |
| US-7,463,862 |
Methods and apparatus to integrate image rejection into quadrature mixers Methods and apparatus to integrate image rejection into quadrature mixers are disclosed. A disclosed image-rejection quadrature mixer comprises a quadrature... |
| US-7,463,700 |
Code division multiple access wireless system with closed loop mode using
ninety degree phase rotation and... A wireless communication system (10). The system comprises a user station (12). The user station comprises despreading circuitry (22) for receiving and... |
| US-7,463,653 |
Apparatus and method for compression of the timing trace stream In a test and debug system, a plurality of trace streams, including a timing trace stream, are transmitted from the target processing unit to the host processing... |
| US-7,463,545 |
System and method for reducing latency in a memory array decoder circuit A system and method are disclosed for reducing latency in asserting a word-line for read/write operations of a memory row in a memory array. One embodiment of... |
| US-7,463,504 |
Active float for the dummy bit lines in FeRAM Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along... |
| US-7,463,469 |
System and method for current overload response with class D topology A system and method for responding to a current overload condition in a power switch provides a class D topology that applies a current sink or current source to... |
| US-7,463,118 |
Piezoelectric resonator with an efficient all-dielectric Bragg reflector A piezoelectric resonator with an acoustic Bragg reflector that includes alternating layers of high and low acoustic impedance materials. The high and low... |
| US-7,463,075 |
Method and delay circuit with accurately controlled duty cycle A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal... |
| US-7,463,011 |
Switching regulator with analog or digital control A switching regulator provided according to an aspect of the present invention contains uses one or more error samples from prior iterations, in addition to an... |
| US-7,462,943 |
Semiconductor assembly for improved device warpage and solder ball
coplanarity A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is... |
| US-7,462,783 |
Semiconductor package having a grid array of pin-attached balls Semiconductor chip (1101) of a ball grid array device (1100) is mounted onto tape substrate (1102) using attach adhesive (1103). The metal layer on the top... |
| US-7,462,546 |
Collector tailored structures for integration of binary junction
transistors A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the... |
| US-7,461,367 |
Modifying merged sub-resolution assist features of a photolithographic
mask Modifying merged sub-resolution assist features includes receiving a mask pattern comprising the merged sub-resolution assist features, where a segmenting... |
| US-7,461,283 |
Skip counter for system timer A skip counter timing device employing a typical hardware system timer, a skip counter with a skip count register, a signal gate and a hardware system tick... |
| US-7,460,890 |
Bi-modal RF architecture for low power devices A wireless receiver is provided that includes a component and a power control logic 80. The component is operable to receive a wireless signal and process the... |
| US-7,460,612 |
Method and apparatus for a fully digital quadrature modulator A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art... |
| US-7,460,499 |
Modulation noise estimation mechanism An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a... |
| US-7,460,282 |
Dynamic pattern generation for optical signal processing A processor such as a digital signal processor (DSP) is used to dynamically generate patterns and/or sequences of patterns for a spatial light modulator (SLM),... |
| US-7,460,275 |
Odd/even error diffusion filter An error diffusion method and system to ameliorate the effects of data quantization. The error diffusion method is especially well-suited to display systems that... |
| US-7,460,135 |
Two dimensional rotation of sub-sampled color space images In a method and system for controlling rotation of a color image stored as sub-sampled image data in a memory, a controller includes a finite state machine (FSM)... |
| US-7,460,132 |
System and method for motion adaptive anti-aliasing System and method for processing image data containing motion for display on a display device. A preferred embodiment comprises applying a filter to an input... |
| US-7,459,977 |
Signal transfer circuit and circuit device using same A signal transfer circuit appropriate for use in realizing both high circuit stability and high current driving ability is disclosed. Signal transfer circuit A... |
| US-7,459,926 |
Scan distributor loading scan paths simultaneous with loading test data An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)... |
| US-7,459,891 |
Soft-start circuit and method for low-dropout voltage regulators A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a... |
| US-7,459,734 |
Method for manufacturing and structure for transistors with reduced gate
to contact spacing A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed... |
| US-7,459,402 |
Protection layers in micromirror array devices To protect the structural layers from being eroded in the etching process, a protection layer is deposited on the exposed structural layers of the micromirror.... |
| US-7,459,390 |
Method for forming ultra thin low leakage multi gate devices The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment,... |
| US-7,459,357 |
Versatile system for cross-lateral junction field effect transistor The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage,... |
| US-7,459,339 |
Flip-chip semiconductor device manufacturing method The objective of the invention is to provide a semiconductor device manufacturing method that can suppress the formation of voids in the underfill resin and... |
| US-7,459,333 |
Method for making a micromirror-based projection system with a
programmable control unit for controlling a... A projection system is disclosed herein. The projection system employs a spatial light modulator comprising an array of individually addressable pixels for... |
| US-7,459,325 |
MEMS passivation with transition metals Organic surfactants are employed to passivate the surfaces of MEMS devices, such as digital micromirrors. The binding of these surfactants to the surface is... |
| US-7,458,691 |
Holographic combiners for illumination of spatial light modulators in
projection systems Described is an optical device for combining multiple light sources in an optical projection system. One embodiment of the optical device includes at least two... |
| US-7,458,058 |
Verifying a process margin of a mask pattern using intermediate stage
models Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified... |
| US-7,458,007 |
Error correction structures and methods A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency.... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.