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| Patent # | Description |
|---|---|
| US-7,355,777 |
Energy storage structures using electromechanically active materials for
micro electromechanical systems System and method for storing energy using electromechanically active materials in micro electromechanical systems. A preferred embodiment comprises a movable... |
| US-7,355,655 |
Systems and methods for separating luma and chroma information in a
composite video signal Systems and method are provided for luma-chroma separation. A demodulator system demodulates a composite video signal to produce at least two baseband chroma... |
| US-7,355,430 |
Parallel scan distributors and collectors and process of testing
integrated circuits An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)... |
| US-7,355,255 |
Nickel silicide including indium and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same.... |
| US-7,354,865 |
Method for removal of pattern resist over patterned metal having an
underlying spacer layer A method of removing the pattern resist that remains on a microchip wafer after etching a patterned layer that is supported by a spacer layer. After the etch,... |
| US-7,354,854 |
Nickel silicide method and structure Nickel silicide contact regions are formed on a source (2), drain (3) and polycrystalline silicon gate (5) of an integrated circuit transistor by annealing it... |
| US-7,354,853 |
Selective dry etching of tantalum and tantalum nitride The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in... |
| US-7,353,307 |
Linking addressable shadow port and protocol for serial bus networks Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of... |
| US-7,353,217 |
Intelligent realtime management of processing resources A method and system for ordering a priority for a function to receive any type of processing resources in a system that includes a plurality of functions. The... |
| US-7,352,823 |
Algorithm for computing distances to a received point in an ADSL system Method for computing distances to received data points. A preferred embodiment comprises determining a first point on a grid nearest to the received point,... |
| US-7,352,820 |
DMT system with variable subchannel spacing in TCM ISDN noise A device comprises a first component operable to produce a plurality of discrete multitone symbols based in part on a subchannel spacing and a cyclic extension... |
| US-7,352,818 |
Short and long sequence boundary detection algorithm for wireless LAN
modems A method for detecting a boundary between two sequences in a wireless local area network is presented that permits rapid detection of the boundary. The method... |
| US-7,352,801 |
Selecting one of multiple antennas to receive signals in a wireless packet
network Selecting one of multiple antennas to receive signals in a wireless packet network. Correlation value and gain needed to boost the signal up to a desired power... |
| US-7,352,691 |
Double difference phase detection A method that allows a digital communications system to detect the presence of transmitted messages in noisy environments. The system includes an OFDM... |
| US-7,352,251 |
Systems and methods for suppressing feedback and reference noise in a
phase lock loop circuit Various systems and methods for clock management. As one example, a system for clock management is disclosed that includes a controllable oscillator, an... |
| US-7,352,231 |
Method and circuit for perturbing removable singularities in coupled
translinear loops A translinear network (34) has first (Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4) and second (Q.sub.4, Q.sub.3, Q.sub.5, Q.sub.6) translinear loops. A Trafton-Hastings... |
| US-7,352,228 |
Method and apparatus of a level shifter circuit with duty-cycle correction A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to... |
| US-7,352,169 |
Testing components of I/O paths of an integrated circuit Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal... |
| US-7,352,161 |
Burst-mode switching voltage regulator with ESR compensation System and method for a burst-mode switching voltage regulator with good stability and small output voltage ripple. A preferred embodiment comprises a current... |
| US-7,351,651 |
Structure and method for contact pads having a recessed bondable metal
plug over of copper-metallized... A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the... |
| US-7,351,632 |
Semiconductor CMOS devices and methods with NMOS high-k dielectric formed
prior to core PMOS silicon oxynitride... The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS... |
| US-7,351,626 |
Method for controlling defects in gate dielectrics A method for improving high-.kappa. gate dielectric film (104) properties. The high-.kappa. film (104) is subjected to a two step anneal sequence. The first... |
| US-7,350,293 |
Low profile ball-grid array package for high power A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface... |
| US-7,350,092 |
Data synchronization arrangement A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an... |
| US-7,349,934 |
Processor system and method with combined data left and right shift
operation An integrated circuit device (100) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry... |
| US-7,349,932 |
High performance FIR filter A filter includes a tap multiplication circuit and a tap digital-to-analog ("DAC") unit coupled to the tap multiplication circuit. Further, a plurality of clocks... |
| US-7,349,667 |
Simplified noise estimation and/or beamforming for wireless communications A system and method facilitate estimating noise in a received signal. The received signal is formed of a plurality of tones, such as training tones and data... |
| US-7,349,433 |
Signaling for parameterized quality of service (QoS) support The creation, modification, and deletion of a traffic stream 224 with parameterized QoS expectations between two communicating stations 205 and 207, when there... |
| US-7,349,379 |
Channel normalization Soft estimate normalization for weighted multiantenna high-order modulation data channel together with separate antenna pilot channels using averaging in first... |
| US-7,349,285 |
Dual port memory unit using a single port memory core A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock... |
| US-7,349,237 |
Plateline driver with RAMP rate control A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and... |
| US-7,349,146 |
System and method for hinge memory mitigation System and method for reducing failures due to hinge memory in a microdisplay display system. A preferred embodiment includes setting the state of each... |
| US-7,349,033 |
Systems and methods for correcting color phase error in video systems Systems and methods are provided for correcting color phase error in a video decoder system. A demodulator system demodulates the composite input signal and the... |
| US-7,348,855 |
Bias circuitry for cascode transistor circuit An integrated circuit includes a composite transistor including at least a first transistor of a first technology type having a first group of intrinsic... |
| US-7,348,812 |
Multiphased triangular wave oscillating circuit and switching regulator
using it To oscillate and output multiphased triangular waves with a designed waveform shape, wave crest value, and phase relationship. This multiphased triangular wave... |
| US-7,348,797 |
Functional cells for automated I/O timing characterization of an
integrated circuit Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive... |
| US-7,348,643 |
Semiconductor dual guardring arrangement A semiconductor dual guardring arrangement is provided which is useful during electrostatic discharge (ESD) events as well as during normal operating conditions.... |
| US-7,348,265 |
Semiconductor device having a silicided gate electrode and method of
manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The... |
| US-7,348,232 |
Highly activated carbon selective epitaxial process for CMOS In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a... |
| US-7,348,228 |
Deep buried channel junction field effect transistor (DBCJFET) A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed.... |
| US-7,346,898 |
Method for scheduling processors and coprocessors with bit-masking Multiple coprocessor scheduling of parallel processing steps control with bit arithmetic using a bitmask for each data block buffer indicating next processing... |
| US-7,346,821 |
IC with JTAG port, linking module, and off-chip TAP interface An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP... |
| US-7,346,731 |
High performance and scalable width expansion architecture for fully
parallel CAMs A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example... |
| US-7,346,121 |
Code division multiple access wireless system with closed loop mode using
ninety degree phase rotation and... A wireless communication system (10). The system comprises a user station (12). The user station comprises despreading circuitry (22) for receiving and... |
| US-7,346,113 |
Method and circuit for stop of signals quantized using noise-shaping A system and method are provided for stopping a quantized signal from a noise-shaper with a significantly reduced inband transient, compared to a traditional... |
| US-7,346,100 |
Estimating gain and phase imbalance in upconverting transmitters Estimation of gain and phase imbalance of an upconverting transmitter. A transmitter transmits symbols containing vector components of pre-specific relationship... |
| US-7,346,026 |
4X design for wireless local area network throughput enhancement A system and method for wireless local area network throughput enhancement includes an access point and an endpoint station in a wireless computer network... |
| US-7,346,005 |
Adaptive playout of digital packet audio with packet format independent
jitter removal In order to reduce distortion in playout of audio received in a packet over a packet network, the playout unit needs to determine the relative delay of adjacent... |
| US-7,346,003 |
Method of increasing noise immunity with a simulated preamble Circuitry and method for receiving and decoding a data stream without a preamble transmitted from the transmitting device. The invention includes circuitry in... |
| US-7,345,807 |
Laminated package A system and method of aligning a micromirror array to the micromirror package and the micromirror package to a display system. One embodiment provides a method... |
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