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Searching: texas instruments
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| Patent # | Description |
|---|---|
| US-7,242,565 |
Thermal shut-down circuit A primary current circuit 42 that outputs a primary current IPTAT proportional to the primary coefficient of temperature, secondary current circuit 43 outputs a... |
| US-7,242,544 |
Apparatus and method for applying write signals for driving a write head An apparatus for applying write signals including a first write signal and a second write signal to write information to a memory device includes a current... |
| US-7,242,515 |
Structure and method for reducing thermal stresses on a torsional hinged
device Method and structure for mounting a torsional hinged device, such as a mirror, having a first TCE (thermal coefficient of expansion) on a substrate having a... |
| US-7,242,330 |
Dynamic compensation of analog-to-digital converter (ADC) offset errors
using filtered PWM A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing... |
| US-7,242,227 |
Common mode stabilization circuit for differential bus networks A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal... |
| US-7,242,211 |
Hierarchical link instruction register core/embedded core wrapper enable
signals A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing... |
| US-7,241,690 |
Method for conditioning a microelectronics device deposition chamber The present invention provides, in one aspect, a method of conditioning a deposition chamber 100. An undercoat is placed on the walls of a deposition chamber 100... |
| US-7,241,663 |
Maskless multiple sheet polysilicon resistor The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor... |
| US-7,241,646 |
Semiconductor device having voltage output function trim circuitry and
method for same In accordance with the teachings of the present invention, a semiconductor device having voltage output function trim circuitry and a method for the same are... |
| US-7,241,141 |
Low contact SiC boat for silicon nitride stress reduction A vertical wafer boat for supporting at least one semiconductor wafer, formed by a process includes forming a plurality of angled support grooves into a... |
| US-7,240,344 |
Register allocation and code spilling using interference graph coloring An improved method is provided for performing register allocation in a compiler. This method determines the allocation of a plurality R of registers of a... |
| US-7,240,277 |
Memory error detection reporting A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects... |
| US-7,240,189 |
Fast resume to normal operation of a computer in a power saving mode A fast resume of a computer from a low power mode to a normal operating mode captures a power down message from the operating system of the computer to devices... |
| US-7,240,120 |
Universal decoder for use in a network media player A media player coupled to a network contains a processor, non-volatile memory, volatile memory, a driver, and input and output ports. The media player receives a... |
| US-7,239,888 |
Wireless network with multi-device class communication capability A wireless device (e.g. an access point) is adapted to communicate wirelessly with a class 1 device and a class 2 device, wherein the class 2 device is capable... |
| US-7,239,664 |
Method for selecting the data rate for PCM upstream transmission A method selects the data rate for pulse code modulation upstream transmission by determining an approximate transmit power before the upstream transmission... |
| US-7,239,437 |
Reduction of open loop jitter and control loop stabilization of a
torsional hinged device by structural... Apparatus and methods for removing jitter and stabilizing the feed back system of a torsional hinged device with minimal changes to the system. The stabilization... |
| US-7,239,436 |
Method for aligning consecutive scan lines on bi-directional scans of a
resonant mirror A method for aligning consecutive scan lines of a mirror based visual system produced by the bi-directional scan of a resonant mirror is disclosed. The actual... |
| US-7,239,204 |
Current shunt instrumentation amplifier with extended bipolar input common
mode range An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a parallel configuration. A first terminal (12) of a first input... |
| US-7,239,108 |
Method for stepper motor position referencing A method for referencing a polyphase stepper motor by monitoring the current step response in at least one driven phase is presented. The coil current step... |
| US-7,238,986 |
Robust DEMOS transistors and method for making the same Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the... |
| US-7,238,623 |
Versatile system for self-aligning deposition equipment The present invention provides a system (100) for aligning a dispensing apparatus (110) utilized within a semiconductor deposition chamber (102). A stationary... |
| US-7,238,567 |
System and method for integrating low schottky barrier metal source/drain According to one embodiment of the invention, a method for integrating low Schottky barrier metal source/drain includes providing a substrate, forming an... |
| US-7,237,234 |
Method for selective solicitation of user assistance in the performance
tuning process A compiler tool is provided to selectively solicit assistance from a programmer in order to improve optimization of code compiled by the compiler. As a program... |
| US-7,237,233 |
Assembly directives for the support of multi-language programming The present invention provides methods for facilitating the sharing of data structures in a software application written using both a high level programming... |
| US-7,237,151 |
Apparatus and method for trace stream identification of a processor reset When a RESET signal is generated in a target processor during a test procedure, a reset sync marker is generated in a program counter trace stream. The reset... |
| US-7,237,121 |
Secure bootloader for securing digital devices A secure bootloader for securing software and systems in a digital device 110 by ensuring only encrypted and authenticated boot software is loaded and executed... |
| US-7,237,081 |
Secure mode for processors supporting interrupts A digital system is provided with a secure mode (3.sup.rd level of privilege) built in a non-invasive way on a processor system that includes a processor core,... |
| US-7,237,071 |
Embedded symmetric multiprocessor system with arbitration control of
access to shared resources A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors includes a single program... |
| US-7,237,065 |
Configurable cache system depending on instruction type A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the... |
| US-7,237,000 |
Speed of execution of a conditional subtract instruction and increasing
the range of operands over which the... A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of... |
| US-7,236,930 |
Method to extend operating range of joint additive and convolutive
compensating algorithms The operating range of joint additive and convolutive compensating method is extended by enhanced channel estimation procedure that adds SNR-dependent inertia... |
| US-7,236,556 |
Synchronising circuit In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronized with the data... |
| US-7,236,552 |
Data transmission A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach... |
| US-7,236,544 |
Enhanced preamble to enable low power detection System and method for enabling the low power detection of a transmitted sequence. A preferred embodiment comprises the replacement of a portion of a preamble... |
| US-7,236,532 |
Method of initializing a communication system with different bandwidth
receivers and transmitters A method of communicating across a channel includes receiving information having a known bandwidth and a known spectrum. The information is preferably in the... |
| US-7,236,511 |
Structured adaptive frequency hopping The invention generally provides a method of intelligent frequency hopping such as in Bluetooth and Home RF networks. The method (100) includes the acts of... |
| US-7,236,396 |
Area efficient implementation of small blocks in an SRAM array An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure... |
| US-7,236,268 |
Adaptive screening in raster image processing of complex pages A method of data processing is described for generating a screened bitmap in an adaptive manner. The page being printed is subdivided into a plurality of smaller... |
| US-7,236,150 |
Transferring data directly between a processor and a spatial light
modulator A method of loading data into a spatial light modulator, in which a software programmable processor stores binary values for the pixels of at least a portion of... |
| US-7,236,055 |
Differential amplifier circuit and method for reducing thermally induced
offsets caused by large differential... An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled... |
| US-7,236,036 |
Apparatus and method for generating pulses An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for... |
| US-7,236,034 |
Self correcting scheme to match pull up and pull down devices The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a... |
| US-7,236,030 |
Method to implement hysteresis in a MOSFET differential pair input stage A simplified comparator circuit (10) having hysteresis and lower power requirements for its implementation. The circuit (10) includes 2 minimum-sized MOSFETs... |
| US-7,236,021 |
Method of controlling slope and dead time in an integrated output buffer
with inductive load A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive... |
| US-7,236,003 |
H-bridge circuit with shoot through current prevention during power-up The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the... |
| US-7,235,958 |
Apparatus and method to synchronize switching frequencies of multiple
power regulators A power supply has a plurality of switching regulators providing a like plurality of regulated output voltages. The oscillators of the switching regulators are... |
| US-7,235,451 |
Drain extended MOS devices with self-aligned floating region and
fabrication methods therefor Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region... |
| US-7,234,121 |
Method of fabricating an integrated circuit to improve soft error
performance The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error... |
| US-7,234,034 |
Self-clocking memory device A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an... |
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