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CMOS device having different amounts of nitrogen in the NMOS gate
dielectric layers and PMOS gate dielectric layers
The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the...
Versatile system for optimizing current gain in bipolar transistor
Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and...
PMD liner nitride films and fabrication methods for improved NMOS
Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress...
Semiconductor CMOS devices and methods with NMOS high-k dielectric formed
prior to core PMOS dielectric formation
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS...
Semiconductor device having multiple work functions and method of
The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor...
MEMS device wafer-level package
A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of...
Statistical method for identifying microcracks in insulators
One embodiment of the invention is a method for evaluating a material such as low-k dielectric, by a stress-generating test tool such as a needle. The evaluation...
Apparatus and method for identification of a new secondary code start
point following a return from a secondary...
When a NEW SECONDARY CODE EXECUTION START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service...
Efficient address generation for Forney's modular periodic interleavers
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is...
Wireless network scheduling data frames including physical layer
A wireless network is disclosed in which individual wireless stations can be configured to implement any of a plurality of physical configurations including...
Dynamic update of quality of service (Qos) parameter set
The present invention provides a system, method, and apparatus for providing improved quality of service in a wireless local area network transmission system,...
Estimating frequency offsets using pilot tones in an OFDM system
A method for estimating carrier frequency offset (CFO) and sampling frequency offset (SFO) in an Orthogonal Frequency Division Multiplexing (OFDM) system having...
Self-biased high voltage level shifter
A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected...
Apparatus and method to compensate for effects of load capacitance on
A power regulator has an output for regulated power that is connected to supply power to a load. The load can have various electrical characteristics, including...
Method of stall detection for stepper motor system
This invention detects a stall in a stepper motor by determining a motor winding current for each stepper pulse and determining if the winding current of a...
Single inductor dual output buck converter
A single-inductor dual-output buck converter facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of...
System and method to increase die stand-off height
In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of...
Hybrid speech coding and system
Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of...
Switchable hybrid design for asymmetric digital subscriber line
A method is provided for accomplishing asymmetric digital subscriber loop classification and the design of passive hybrid networks for each of the classes. The...
Methods and apparatus for selectively updating memory cell arrays
Methods and apparatus for selectively updating memory cells of a memory cell array are provided. The memory cells of each row of the memory cell array are...
Digital-to-analog converter data rate reduction by interleaving and
recombination through mixer switching
A system and method implement very high data rate baseband DACs suitable for wireless applications related to new standards (e.g. Ultra-Wide Band) using CMOS...
Differential comparator with extended common mode voltage range
A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator...
System and method for die attach using a backside heat spreader
According to one embodiment of the invention, a method of die attach includes providing a chip, forming a heat conductive metal layer outwardly from a backside...
Integrated circuit identification
A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor...
Ferroelectric capacitor stack etch cleaning methods
Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor...
Maintaining coherent synchronization between data streams on detection of
Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync...
Decode logic selecting IC scan path parts
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
IC with TAP, STP and lock out controlled output buffer
Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core...
Removing close-in interferers through a feedback loop
System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer...
Interferer detection and channel estimation for wireless communications
System and method for improving performance of digital wireless communications systems in the presence of interferers. A preferred embodiment comprises...
Method and apparatus for channel estimation in a packet based transmission
system having reduced complexity
A method and apparatus for deriving the channel estimation within a packet based transmission system having a predetermined number of tones (N), wherein each...
Multi-path interference cancellation for transmit diversity
The present invention provides an apparatus, system and method for removal of interference due to multi-path for multiple transmit antennas (hereinafter referred...
Retransmission techniques for enhanced performance in fading wireless
A desired bit sequence (x) can be communicated over a wireless communication link (15) by including the desired bit sequence in each of a plurality of...
Wireless communication system operating in response in part to time
signals from the global position satellite...
A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator...
Orthogonal frequency division multiplexing system with differing control
parameters corresponding to different...
A wireless transmitter (TX.sub.1). The transmitter comprises circuitry for providing a plurality of control (CONTROL) bits and circuitry for providing a...
Apparatus and method for adjusting the resonant frequency of an
A method for increasing the resonant frequency of a torsional hinged device having a reduced attaching area between the torsional hinges and the supporting...
Image sensor with digital output and inherent pixel non-uniformity
The image sensing device provides a digital output for each pixel. As charge builds up in a pixel, the pixel output increases until it reaches a reference level....
System and method for accurate negative bias temperature instability
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal...
Adjustable compensation of a piezo drive amplifier depending on mode and
number of elements driven
An integrated circuit (42) provides drive signals to a piezo element (48) of a milli-actuator device (20) in a mass data storage device (10). The integrated...
Structure and method for bond pads of copper-metallized integrated
A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The...
Transistor fabrication methods using dual sidewall spacers
Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure...
Method of fabricating an epitaxial silicon-germanium layer and an
integrated semiconductor device comprising an...
A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped...
Integrated lamp and aperture alignment method and system
According to one embodiment a method for aligning a light source includes providing a lamp and a lamp interface. The lamp interface has an alignment aperture...
Bond capillary design for ribbon wire bonding
A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an...
Design method and system for optimum performance in integrated circuits
that use power management
The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic...
Method for reducing SRAM test time by applying power-up state knowledge
Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic...
Methods and systems to reduce data skew in FIFOs
The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a...
System and method of implementing variable loop gain in an optical
wireless link based on distance
A system and method of varying the control loop gain of an optical wireless communication link between a transmitting station and a receiving station as an...
Hardware acceleration for reassembly of message packets in a universal
serial bus peripheral device
A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB...
Deflection mechanisms in micromirror devices
A method and apparatus for operating spatial light modulator have been disclosed herein. The spatial light modulator comprises an array of micromirror devices,...