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Patent # Description
US-7,230,868 Stable source-coupled sense amplifier
An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of...
US-7,230,656 Sequential color filter
A sequential color filter and display system. The sequential color filter comprising: a set of at least three color filters (102). The color filters can be...
US-7,230,481 System and method for reducing audible artifacts in an audio system
An amplifier system can include a biasing amplifier that provides a first amplified signal to a DC blocking element that is connected with a load based on a...
US-7,230,473 Precise and process-invariant bandgap reference circuit and method
A voltage generation circuit generates a reference voltage using a bandgap reference. A countering circuit is included to adaptively counter for any deviations...
US-7,230,452 Driver circuit
A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state...
US-7,230,447 Fault tolerant selection of die on wafer
Integrated circuit die on wafer are electronically selected for testing using circuitry (161, 201, PA1 PA4) provided on the wafer.
US-7,230,325 Encapsulation for particle entrapment
A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents...
US-7,229,873 Process for manufacturing dual work function metal gates in a microelectronics device
The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS...
US-7,229,871 Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors
A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate...
US-7,229,869 Method for manufacturing a semiconductor device using a sidewall spacer etchback
The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for...
US-7,228,865 FRAM capacitor stack clean
An embodiment of the invention is a method of cleaning a material stack 2 that has a hard mask top layer 8. The method involves cleaning the material stack 2...
US-7,228,730 Pressure-measuring glow plug
A pressure-measuring glow plug for a diesel engine with a plug body (3, 4) for insertion into a cylinder of the diesel engine, a heating rod (1) which is...
US-7,228,193 Methods for detecting structure dependent process defects
Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies...
US-7,227,949 Separate self-synchronizing packet-based scrambler having replay variation
A separated synchronizing scrambler/descrambler pair that removes the possibility of catastrophic error due to improper transmission of initial condition...
US-7,227,404 Method for preventing regulated supply undershoot in state retained latches of a leakage controlled system...
A system and method are implemented for preventing regulated supply undershoot in state retained latches of a leakage controlled system, using a voltage source...
US-7,227,241 Integrated stacked capacitor and method of fabricating same
An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric...
US-7,227,201 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers
The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the...
US-7,226,835 Versatile system for optimizing current gain in bipolar transistor structures
Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and...
US-7,226,834 PMD liner nitride films and fabrication methods for improved NMOS performance
Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress...
US-7,226,830 Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS...
US-7,226,826 Semiconductor device having multiple work functions and method of manufacture therefor
The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor...
US-7,226,810 MEMS device wafer-level package
A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of...
US-7,225,681 Statistical method for identifying microcracks in insulators
One embodiment of the invention is a method for evaluating a material such as low-k dielectric, by a stress-generating test tool such as a needle. The evaluation...
US-7,225,365 Apparatus and method for identification of a new secondary code start point following a return from a secondary...
When a NEW SECONDARY CODE EXECUTION START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service...
US-7,225,306 Efficient address generation for Forney's modular periodic interleavers
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is...
US-7,224,704 Wireless network scheduling data frames including physical layer configuration
A wireless network is disclosed in which individual wireless stations can be configured to implement any of a plurality of physical configurations including...
US-7,224,679 Dynamic update of quality of service (Qos) parameter set
The present invention provides a system, method, and apparatus for providing improved quality of service in a wireless local area network transmission system,...
US-7,224,666 Estimating frequency offsets using pilot tones in an OFDM system
A method for estimating carrier frequency offset (CFO) and sampling frequency offset (SFO) in an Orthogonal Frequency Division Multiplexing (OFDM) system having...
US-7,224,202 Self-biased high voltage level shifter
A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected...
US-7,224,153 Apparatus and method to compensate for effects of load capacitance on power regulator
A power regulator has an output for regulated power that is connected to supply power to a load. The load can have various electrical characteristics, including...
US-7,224,140 Method of stall detection for stepper motor system
This invention detects a stall in a stepper motor by determining a motor winding current for each stepper pulse and determining if the winding current of a...
US-7,224,085 Single inductor dual output buck converter
A single-inductor dual-output buck converter facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of...
US-7,224,071 System and method to increase die stand-off height
In accordance with the present invention, a system and method to increase die stand-off height in a flip chip are provided. The system includes a plurality of...
US-7,222,070 Hybrid speech coding and system
Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of...
US-7,221,754 Switchable hybrid design for asymmetric digital subscriber line
A method is provided for accomplishing asymmetric digital subscriber loop classification and the design of passive hybrid networks for each of the classes. The...
US-7,221,498 Methods and apparatus for selectively updating memory cell arrays
Methods and apparatus for selectively updating memory cells of a memory cell array are provided. The memory cells of each row of the memory cell array are...
US-7,221,300 Digital-to-analog converter data rate reduction by interleaving and recombination through mixer switching
A system and method implement very high data rate baseband DACs suitable for wireless applications related to new standards (e.g. Ultra-Wide Band) using CMOS...
US-7,221,190 Differential comparator with extended common mode voltage range
A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator...
US-7,221,055 System and method for die attach using a backside heat spreader
According to one embodiment of the invention, a method of die attach includes providing a chip, forming a heat conductive metal layer outwardly from a backside...
US-7,220,606 Integrated circuit identification
A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor...
US-7,220,600 Ferroelectric capacitor stack etch cleaning methods
Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor...
US-7,219,333 Maintaining coherent synchronization between data streams on detection of overflow
Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync...
US-7,219,284 Decode logic selecting IC scan path parts
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,219,283 IC with TAP, STP and lock out controlled output buffer
Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core...
US-7,218,904 Removing close-in interferers through a feedback loop
System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer...
US-7,218,894 Interferer detection and channel estimation for wireless communications networks
System and method for improving performance of digital wireless communications systems in the presence of interferers. A preferred embodiment comprises...
US-7,218,693 Method and apparatus for channel estimation in a packet based transmission system having reduced complexity
A method and apparatus for deriving the channel estimation within a packet based transmission system having a predetermined number of tones (N), wherein each...
US-7,218,692 Multi-path interference cancellation for transmit diversity
The present invention provides an apparatus, system and method for removal of interference due to multi-path for multiple transmit antennas (hereinafter referred...
US-7,218,680 Retransmission techniques for enhanced performance in fading wireless communication channels
A desired bit sequence (x) can be communicated over a wireless communication link (15) by including the desired bit sequence in each of a plurality of...
US-7,218,669 Wireless communication system operating in response in part to time signals from the global position satellite...
A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator...
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