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Patent # Description
US-7,212,139 System for suppressing aliasing interferers in decimating and sub-sampling systems
A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is...
US-7,212,059 Level shift circuit
The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are...
US-7,212,023 System and method for accurate negative bias temperature instability characterization
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal...
US-7,211,842 System with meshed power and signal buses on cell array
A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a...
US-7,211,516 Nickel silicide including indium and a method of manufacture therefor
The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same....
US-7,211,481 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer
The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while...
US-7,210,078 Error bit method and circuitry for oscillation-based characterization
A method for evaluating an output of a sequential circuit 2 by storing a series of output pulses from the sequential circuit 2 and determining whether the output...
US-7,210,072 Apparatus and method for trace stream identification of a pipeline flattener primary code flush following...
When a PROGRAM CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The...
US-7,209,513 Phase, frequency and gain characterization and mitigation in SCDMA burst receiver using multi-pass processing
A method and apparatus provide phase, frequency and gain characterization and mitigation in a synchronized code division multiple access (SCDMA) burst receiver...
US-7,209,467 Adaptive adjustment of backoff times in wireless network communications
A wireless network, including a plurality of network elements such as a wireless access point (9), and computer stations (2, 4, 6), is disclosed. The wireless...
US-7,209,060 Reducing variation in reference voltage when the load varies dynamically
Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference...
US-7,209,058 Trace receiver data compression
A method repacks variable width trace data into a different packet length previous to being stored into memory. In order to conserve bandwidth, the trace data...
US-7,209,005 Class-AB amplifier for dual voltage supplies
An amplifier providing a drive signal indicative of a data input signal to a capacitive and/or resistive type load, the amplifier having a first transistor...
US-7,208,993 Input current leakage correction for multi-channel LVDS front multiplexed repeaters
A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of...
US-7,208,409 Integrated circuit metal silicide method
Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing...
US-7,208,398 Metal-halogen physical vapor deposition for semiconductor device defect reduction
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by...
US-7,208,388 Thin film resistor head structure and method for reducing head resistivity variance
A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce...
US-7,208,386 Drain extended MOS transistor with improved breakdown robustness
A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures...
US-7,208,380 Interface improvement by stress application during oxide growth through use of backside films
The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a...
US-7,208,379 Pitch multiplication process
A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the...
US-7,208,364 Methods of fabricating high voltage devices
Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well...
US-7,208,362 Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to...
US-7,208,330 Method for varying the uniformity of a dopant as it is placed in a substrate by varying the speed of the...
The present invention provides a method for placing a dopant in a substrate and a method for manufacturing an integrated circuit. The method for placing a dopant...
US-7,207,678 Prism for high contrast projection
Prism elements having TIR surfaces placed in close proximity to the active area of a SLM device to separate unwanted off-state and/or flat-state light from the...
US-7,206,734 Exporting on-chip data processor trace information with variable proportions of control and data
Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into...
US-7,206,155 High-speed, low power preamplifier write driver
A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control...
US-7,206,030 Fast-convergence two-stage automatic gain control (AGC)
Disclosed are methods and systems for automatic gain control (AGC) in circuits. The disclosed methods and systems provide accurate and rapidly converging...
US-7,205,924 Circuit for high-resolution phase detection in a digital RF processor
A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor....
US-7,205,833 Method and circuit for reduced setting time in an amplifier
An improved method and circuit for reduced settling time in an amplifier are provided. The amplifier comprises a composite amplifier circuit including a first...
US-7,205,809 Low power bus-hold circuit
A low power bus hold circuit includes: a first inverter having an input coupled to a bus hold input node; and a second inverter having a first input coupled to a...
US-7,205,749 Power line communication using power factor correction circuits
A PFC circuit modulating a power line using pulse width modulation (PWM) to drive a power MOSFET and series inductor across the power line. Since many modern...
US-7,205,736 Method for voltage feedback for current mode linear motor driver
Methods and systems for driving a motor are disclosed. A center tap voltage and a desired center tap voltage are used to generate a voltage feedback. A power...
US-7,203,880 Generating an abbreviated netlist including pseudopin inputs and output nodes
A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary...
US-7,203,803 Overflow protected first-in first-out architecture
An electronic device (10). The device comprises an input (16.sub.I) for receiving successive data words, wherein each data word of the successive data words...
US-7,203,797 Memory management of local variables
A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each...
US-7,203,460 Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit
An automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20)...
US-7,203,425 Optical wireless link
An optical, line-of-sight modem. The modem includes a micro-mirror assembly including a micro-mirror and including an actuator for providing rotational movement...
US-7,203,398 Compact DMD-based optical module
An optical module having an integral optical waveguide with waveguide ports at each end. The optical waveguide receives an input light beam through a first...
US-7,203,373 Image and video coding with redundant run-length-level-last codewords removed
A method of run-length encoding for known block size, such as image/video compression with block transform, such as DCT, with end of block indication suppressed...
US-7,203,237 Transcoders and methods
Transcoding as from MPEG-2 SDTV to MPEG-4 CIF reuses motion vectors and downsamples in the frequency (DCT) domain with differing treatments of frame-DCT and...
US-7,203,177 Bandwidth efficient conferencing system with distributed processing
A distributed intelligence conferencing system is disclosed, having a plurality of conferencing nodes to connect groups of participants to a conference. Each of...
US-7,202,974 Efficient under color removal
A method of performing color space conversion and under color removal. Pixelated data is first resampled (102) to an efficient word size--typically 8-bits wide....
US-7,202,877 Sprite rendering
Computation of sprite position and size in JSR-184 with revised modelview matrix made with column vector lengths of original modelview matrix.
US-7,202,729 Methods and apparatus to bias the backgate of a power switch
Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch...
US-7,202,710 Apparatus and method for handling interdevice signaling
An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus...
US-7,202,643 High efficiency DC-to-DC synchronous buck converter
A DC-to-DC power regulator circuit, such as a synchronous buck DC-to-DC converter circuit, having improved efficiency. A power stage is provided, having an input...
US-7,202,537 Versatile system for limiting electric field degradation of semiconductor structures
The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from...
US-7,202,533 Thin film resistors integrated at a single metal interconnect level of die
An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric...
US-7,200,835 Method of locating sub-resolution assist feature(s)
A method of operating a computing system to determine reticle data. The reticle data is for completing a reticle for use in projecting an image to a...
US-7,200,783 Removable and replaceable TAP domain selection circuitry
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is...
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