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Patent # Description
US-7,205,736 Method for voltage feedback for current mode linear motor driver
Methods and systems for driving a motor are disclosed. A center tap voltage and a desired center tap voltage are used to generate a voltage feedback. A power...
US-7,203,880 Generating an abbreviated netlist including pseudopin inputs and output nodes
A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary...
US-7,203,803 Overflow protected first-in first-out architecture
An electronic device (10). The device comprises an input (16.sub.I) for receiving successive data words, wherein each data word of the successive data words...
US-7,203,797 Memory management of local variables
A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each...
US-7,203,460 Automated test of receiver sensitivity and receiver jitter tolerance of an integrated circuit
An automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20)...
US-7,203,425 Optical wireless link
An optical, line-of-sight modem. The modem includes a micro-mirror assembly including a micro-mirror and including an actuator for providing rotational movement...
US-7,203,398 Compact DMD-based optical module
An optical module having an integral optical waveguide with waveguide ports at each end. The optical waveguide receives an input light beam through a first...
US-7,203,373 Image and video coding with redundant run-length-level-last codewords removed
A method of run-length encoding for known block size, such as image/video compression with block transform, such as DCT, with end of block indication suppressed...
US-7,203,237 Transcoders and methods
Transcoding as from MPEG-2 SDTV to MPEG-4 CIF reuses motion vectors and downsamples in the frequency (DCT) domain with differing treatments of frame-DCT and...
US-7,203,177 Bandwidth efficient conferencing system with distributed processing
A distributed intelligence conferencing system is disclosed, having a plurality of conferencing nodes to connect groups of participants to a conference. Each of...
US-7,202,974 Efficient under color removal
A method of performing color space conversion and under color removal. Pixelated data is first resampled (102) to an efficient word size--typically 8-bits wide....
US-7,202,877 Sprite rendering
Computation of sprite position and size in JSR-184 with revised modelview matrix made with column vector lengths of original modelview matrix.
US-7,202,729 Methods and apparatus to bias the backgate of a power switch
Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch...
US-7,202,710 Apparatus and method for handling interdevice signaling
An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus...
US-7,202,643 High efficiency DC-to-DC synchronous buck converter
A DC-to-DC power regulator circuit, such as a synchronous buck DC-to-DC converter circuit, having improved efficiency. A power stage is provided, having an input...
US-7,202,537 Versatile system for limiting electric field degradation of semiconductor structures
The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from...
US-7,202,533 Thin film resistors integrated at a single metal interconnect level of die
An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric...
US-7,200,835 Method of locating sub-resolution assist feature(s)
A method of operating a computing system to determine reticle data. The reticle data is for completing a reticle for use in projecting an image to a...
US-7,200,783 Removable and replaceable TAP domain selection circuitry
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is...
US-7,200,782 Clock recovery system for encoded serial data with simplified logic and jitter tolerance
The present invention facilitates clock and data recovery for serial data streams by selecting a clock phase for each input data transition and generating a...
US-7,200,767 Maintaining synchronization of multiple data channels with a common clock signal
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g.,...
US-7,200,730 Method of operating a memory at high speed using a cycle ready status output signal
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an...
US-7,200,690 Memory access system providing increased throughput rates when accessing large volumes of data by determining...
Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the...
US-7,200,498 System for remediating cross contamination in semiconductor manufacturing processes
The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. According to the present invention,...
US-7,200,404 Information storage to support wireless communication in non-exclusive spectrum
Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum...
US-7,200,372 Reduction of dynamic DC offsets in a wireless receiver
A gain control system in a Direct Conversion Receiver or similar receiver, includes an automatic gain control circuit which determines whether a low noise...
US-7,200,196 Interpolation based timing recovery
The present invention provides a solution that eliminates both the voltage-controlled oscillator ("VXCO" 105) and its associated D/A converter (120) from the...
US-7,200,182 Space time block coded transmit antenna diversity for WCDMA
A circuit comprising a channel encoder circuit coupled to receive an input data sequence and produce an output data sequence. An interleaver circuit coupled to...
US-7,200,178 Methods for optimizing time variant communication channels
Methods and apparatus for optimizing wireless communications channels by employing multi-channel modulation techniques in wireless communication systems is...
US-7,200,027 Ferroelectric memory reference generator systems using staging capacitors
Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric...
US-7,199,917 Micro-mirror element with double binge
According to one embodiment of the present invention a micro-mirror element comprises a lower layer, a first middle layer, a second middle layer, and a...
US-7,199,621 Low AC impedance input stage for fast startup applications
The low AC impedance input stage circuit for fast startup applications includes: a first transistor coupled between a first input node and a first output node; a...
US-7,199,613 Reducing coupling effect on reference voltages when output buffers implemented with low voltage transistors...
Reducing the effect of coupling on a reference voltage received at a node of an output buffer, wherein the effect of coupling is due to the transitions in the...
US-7,199,563 DC-DC converter
The object of this invention is to improve efficiency in the step-up/down mode and eliminate ringing in the output voltage when switching between the step-up...
US-7,199,471 Method and apparatus for reducing capacitive coupling between lines in an integrated circuit
An integrated circuit (78) includes a memory circuit (10, 110, 210, 310, 410) having a group of bitlines (21 28, 121 128, 221 228, 321 328, 421 428), and having...
US-7,199,430 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-7,199,047 Bi-layer etch stop process for defect reduction and via stress migration improvement
A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric...
US-7,199,032 Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small...
US-7,199,021 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication
The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape...
US-7,199,020 Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices
A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor...
US-7,199,011 Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon
The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced...
US-7,198,993 Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted...
A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2)...
US-7,198,982 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,198,705 Plating-rinse-plating process for fabricating copper interconnects
An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer...
US-7,197,921 System and method for detecting motion of an object
Systems and methods are disclosed to for detecting movement of an object. In one embodiment, a system is disclosed to detect movement of an object (e.g., a...
US-7,197,733 Integrated circuit dynamic parameter management in response to dynamic energy evaluation
A single integrated circuit (12). The integrated circuit comprises a first circuit (14.sub.x) having a data path, the first circuit consisting of a first number...
US-7,197,730 Reducing time to design integrated circuits including performing electro-migration check
The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or...
US-7,197,623 Multiple processor cellular radio
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is...
US-7,197,524 Direct RF sampling for cable applications and other broadband signals
A sampling method implements direct RF sampling of the down-stream DOCSIS and Euro-DOCSIS cable plant signals present at the customer premises equipment (CPE).
US-7,197,453 System and method for optimizing the operation of an oversampled discrete Fourier transform filter bank
A system for, and method of optimizing an operation of an oversampled filter bank and an oversampled discrete Fourier transform (DFT) filter bank designed by the...
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