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Patent # Description
US-7,222,070 Hybrid speech coding and system
Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of...
US-7,221,754 Switchable hybrid design for asymmetric digital subscriber line
A method is provided for accomplishing asymmetric digital subscriber loop classification and the design of passive hybrid networks for each of the classes. The...
US-7,221,498 Methods and apparatus for selectively updating memory cell arrays
Methods and apparatus for selectively updating memory cells of a memory cell array are provided. The memory cells of each row of the memory cell array are...
US-7,221,300 Digital-to-analog converter data rate reduction by interleaving and recombination through mixer switching
A system and method implement very high data rate baseband DACs suitable for wireless applications related to new standards (e.g. Ultra-Wide Band) using CMOS...
US-7,221,190 Differential comparator with extended common mode voltage range
A system and method is provided for extending the range of a common mode voltage of a differential comparator. In one embodiment, a differential comparator...
US-7,221,055 System and method for die attach using a backside heat spreader
According to one embodiment of the invention, a method of die attach includes providing a chip, forming a heat conductive metal layer outwardly from a backside...
US-7,220,606 Integrated circuit identification
A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor...
US-7,220,600 Ferroelectric capacitor stack etch cleaning methods
Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor...
US-7,219,333 Maintaining coherent synchronization between data streams on detection of overflow
Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync...
US-7,219,284 Decode logic selecting IC scan path parts
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan...
US-7,219,283 IC with TAP, STP and lock out controlled output buffer
Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core...
US-7,218,904 Removing close-in interferers through a feedback loop
System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer...
US-7,218,894 Interferer detection and channel estimation for wireless communications networks
System and method for improving performance of digital wireless communications systems in the presence of interferers. A preferred embodiment comprises...
US-7,218,693 Method and apparatus for channel estimation in a packet based transmission system having reduced complexity
A method and apparatus for deriving the channel estimation within a packet based transmission system having a predetermined number of tones (N), wherein each...
US-7,218,692 Multi-path interference cancellation for transmit diversity
The present invention provides an apparatus, system and method for removal of interference due to multi-path for multiple transmit antennas (hereinafter referred...
US-7,218,680 Retransmission techniques for enhanced performance in fading wireless communication channels
A desired bit sequence (x) can be communicated over a wireless communication link (15) by including the desired bit sequence in each of a plurality of...
US-7,218,669 Wireless communication system operating in response in part to time signals from the global position satellite...
A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator...
US-7,218,604 Orthogonal frequency division multiplexing system with differing control parameters corresponding to different...
A wireless transmitter (TX.sub.1). The transmitter comprises circuitry for providing a plurality of control (CONTROL) bits and circuitry for providing a...
US-7,218,439 Apparatus and method for adjusting the resonant frequency of an oscillating device
A method for increasing the resonant frequency of a torsional hinged device having a reduced attaching area between the torsional hinges and the supporting...
US-7,218,350 Image sensor with digital output and inherent pixel non-uniformity suppression
The image sensing device provides a digital output for each pixel. As charge builds up in a pixel, the pixel output increases until it reaches a reference level....
US-7,218,132 System and method for accurate negative bias temperature instability characterization
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal...
US-7,218,029 Adjustable compensation of a piezo drive amplifier depending on mode and number of elements driven
An integrated circuit (42) provides drive signals to a piezo element (48) of a milli-actuator device (20) in a mass data storage device (10). The integrated...
US-7,217,656 Structure and method for bond pads of copper-metallized integrated circuits
A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The...
US-7,217,626 Transistor fabrication methods using dual sidewall spacers
Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure...
US-7,217,322 Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an...
A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped...
US-7,216,990 Integrated lamp and aperture alignment method and system
According to one embodiment a method for aligning a light source includes providing a lamp and a lamp interface. The lamp interface has an alignment aperture...
US-7,216,794 Bond capillary design for ribbon wire bonding
A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an...
US-7,216,310 Design method and system for optimum performance in integrated circuits that use power management
The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic...
US-7,216,272 Method for reducing SRAM test time by applying power-up state knowledge
Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic...
US-7,216,247 Methods and systems to reduce data skew in FIFOs
The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a...
US-7,215,888 System and method of implementing variable loop gain in an optical wireless link based on distance
A system and method of varying the control loop gain of an optical wireless communication link between a transmitting station and a receiving station as an...
US-7,215,670 Hardware acceleration for reassembly of message packets in a universal serial bus peripheral device
A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB...
US-7,215,458 Deflection mechanisms in micromirror devices
A method and apparatus for operating spatial light modulator have been disclosed herein. The spatial light modulator comprises an array of micromirror devices,...
US-7,215,271 Method and apparatus for forming transient response characteristics
Transient response generating circuit A has a first circuit 3 that generates transient response OUT1 in a first polarity direction, a second circuit 4 that...
US-7,215,202 Programmable gain amplifier and method
One embodiment of the present invention may include a programmable gain amplifier comprising an input multiplexer operative to sequentially select input signals...
US-7,215,201 Integrated circuit having a low power, gain-enhanced, low noise amplifying circuit
An amplifying circuit includes an n-type transistor having a source, a gate coupled to a first bias voltage, and a drain coupled to a first supply voltage...
US-7,215,185 Threshold voltage extraction for producing a ramp signal with reduced process sensitivity
A system for providing a threshold voltage (V.sub.T) includes a V.sub.T extractor that extracts the V.sub.T for a MOS transistor relative to a first voltage...
US-7,215,000 Selectively encased surface metal structures in a semiconductor device
The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105)...
US-7,214,609 Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity...
US-7,214,607 Compliant wirebond pedestal
A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906)....
US-7,214,550 Method to produce thin film resistor using dry etch
A method of fabricating a thin film resistor (100). The resistor material (104), e.g., NiCr, is deposited. A hard mask material (106), e.g., TiW, may be...
US-7,213,184 Testing of modules operating with different characteristics of control signals using scan based techniques
Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules...
US-7,213,171 IEEE 1149.1 tap instruction scan with augmented TLM scan mode
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-7,212,931 Electric energy meter for an AC mains supply
An energy consumption meter having a variable phase error compensator. While the variable phase error compensator may provide fixed phase error compensation for...
US-7,212,607 X-ray confocal defect detection systems and methods
An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a...
US-7,212,387 Electrostatic discharge protection device including precharge reduction
ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge...
US-7,212,359 Color rendering of illumination light in display systems
A method and a color rendering filter for compensating for deficiency in illumination light from a light source in display systems are provided. The color...
US-7,212,139 System for suppressing aliasing interferers in decimating and sub-sampling systems
A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is...
US-7,212,059 Level shift circuit
The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are...
US-7,212,023 System and method for accurate negative bias temperature instability characterization
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal...
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