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Patent # Description
US-7,200,782 Clock recovery system for encoded serial data with simplified logic and jitter tolerance
The present invention facilitates clock and data recovery for serial data streams by selecting a clock phase for each input data transition and generating a...
US-7,200,767 Maintaining synchronization of multiple data channels with a common clock signal
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g.,...
US-7,200,730 Method of operating a memory at high speed using a cycle ready status output signal
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an...
US-7,200,690 Memory access system providing increased throughput rates when accessing large volumes of data by determining...
Enhancing the throughput rate of a memory access system by using store and forward buffers (SFB) in combination with a DMA engine. According to an aspect of the...
US-7,200,498 System for remediating cross contamination in semiconductor manufacturing processes
The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. According to the present invention,...
US-7,200,404 Information storage to support wireless communication in non-exclusive spectrum
Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum...
US-7,200,372 Reduction of dynamic DC offsets in a wireless receiver
A gain control system in a Direct Conversion Receiver or similar receiver, includes an automatic gain control circuit which determines whether a low noise...
US-7,200,196 Interpolation based timing recovery
The present invention provides a solution that eliminates both the voltage-controlled oscillator ("VXCO" 105) and its associated D/A converter (120) from the...
US-7,200,182 Space time block coded transmit antenna diversity for WCDMA
A circuit comprising a channel encoder circuit coupled to receive an input data sequence and produce an output data sequence. An interleaver circuit coupled to...
US-7,200,178 Methods for optimizing time variant communication channels
Methods and apparatus for optimizing wireless communications channels by employing multi-channel modulation techniques in wireless communication systems is...
US-7,200,027 Ferroelectric memory reference generator systems using staging capacitors
Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric...
US-7,199,917 Micro-mirror element with double binge
According to one embodiment of the present invention a micro-mirror element comprises a lower layer, a first middle layer, a second middle layer, and a...
US-7,199,621 Low AC impedance input stage for fast startup applications
The low AC impedance input stage circuit for fast startup applications includes: a first transistor coupled between a first input node and a first output node; a...
US-7,199,613 Reducing coupling effect on reference voltages when output buffers implemented with low voltage transistors...
Reducing the effect of coupling on a reference voltage received at a node of an output buffer, wherein the effect of coupling is due to the transitions in the...
US-7,199,563 DC-DC converter
The object of this invention is to improve efficiency in the step-up/down mode and eliminate ringing in the output voltage when switching between the step-up...
US-7,199,471 Method and apparatus for reducing capacitive coupling between lines in an integrated circuit
An integrated circuit (78) includes a memory circuit (10, 110, 210, 310, 410) having a group of bitlines (21 28, 121 128, 221 228, 321 328, 421 428), and having...
US-7,199,430 Advanced CMOS using super steep retrograde wells
The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer...
US-7,199,047 Bi-layer etch stop process for defect reduction and via stress migration improvement
A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric...
US-7,199,032 Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small...
US-7,199,021 Methods and systems to mitigate etch stop clipping for shallow trench isolation fabrication
The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape...
US-7,199,020 Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices
A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor...
US-7,199,011 Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon
The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced...
US-7,198,993 Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted...
A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2)...
US-7,198,982 Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates
A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from...
US-7,198,705 Plating-rinse-plating process for fabricating copper interconnects
An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer...
US-7,197,921 System and method for detecting motion of an object
Systems and methods are disclosed to for detecting movement of an object. In one embodiment, a system is disclosed to detect movement of an object (e.g., a...
US-7,197,733 Integrated circuit dynamic parameter management in response to dynamic energy evaluation
A single integrated circuit (12). The integrated circuit comprises a first circuit (14.sub.x) having a data path, the first circuit consisting of a first number...
US-7,197,730 Reducing time to design integrated circuits including performing electro-migration check
The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or...
US-7,197,623 Multiple processor cellular radio
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is...
US-7,197,524 Direct RF sampling for cable applications and other broadband signals
A sampling method implements direct RF sampling of the down-stream DOCSIS and Euro-DOCSIS cable plant signals present at the customer premises equipment (CPE).
US-7,197,453 System and method for optimizing the operation of an oversampled discrete Fourier transform filter bank
A system for, and method of optimizing an operation of an oversampled filter bank and an oversampled discrete Fourier transform (DFT) filter bank designed by the...
US-7,197,067 Parameter selection in a communication system
A method is provided for automatically optimizing parameter selection in a communication system having one or more channels for transmitting and receiving...
US-7,197,045 CMTS architecture based on ethernet interface locatable in a fiber node
A communication device (116, 216, 316, 416) for a communications network having a first integrated circuit (IC) (141, 244, 344, 444) including one or more...
US-7,196,917 PFC pre-regulator frequency dithering circuit
A circuit and method of dithering the switching frequency of an off-line power factor corrected (PFC) pre-regulator. The circuitry used to dither the frequency...
US-7,196,890 Electrostatic discharge protection power rail clamp with feedback-enhanced triggering and conditioning circuitry
Electrostatic discharge protection circuitry includes a timing circuit operably coupled between the high supply side and low supply side of an associated...
US-7,196,887 PMOS electrostatic discharge (ESD) protection device
A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A...
US-7,196,740 Projection TV with improved micromirror array
In order to minimize light diffraction along the direction of switching and more particularly light diffraction into the acceptance cone of the collection...
US-7,196,684 Spatial light modulator with charge-pump pixel cell
A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the...
US-7,196,643 Resolver arrangement
A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing...
US-7,196,640 Relaxation oscillator based keypad decoder
The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC...
US-7,196,585 Fast-response current limiting
An amplifier (10'') has a first amplifier stage (14) for producing a control current (I.sub.X) in response to an input voltage. A second amplifier stage (16) has...
US-7,196,581 Amplifier switching control circuit and method for current shunt instrumentation amplifier having extended...
An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through...
US-7,196,564 High frequency balanced phase interpolator
A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase...
US-7,196,398 Resistor integration structure and technique for noise elimination
A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate...
US-7,196,338 Ultra-thin sample preparation for transmission electron microscopy
In accordance with the invention, there is a method of fabricating a material for transmission electron microscopy comprising removing a first portion from a...
US-7,196,309 Photodetection circuit
In a photo detection arrangement, the current through a detector 10 is sensed by a series resistor Rs and amplified and amplified at 21. The output of the...
US-7,195,984 Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit...
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively...
US-7,195,965 Premature breakdown in submicron device geometries
The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502,...
US-7,195,954 Low capacitance coupling wire bonded semiconductor device
A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a...
US-7,195,679 Versatile system for wafer edge remediation
The present invention provides a system (200, 300) for remediating aberrations along the perimeter of a semiconductor wafer (202). The system includes a cleaning...
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