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Patent # Description
US-7,197,067 Parameter selection in a communication system
A method is provided for automatically optimizing parameter selection in a communication system having one or more channels for transmitting and receiving...
US-7,197,045 CMTS architecture based on ethernet interface locatable in a fiber node
A communication device (116, 216, 316, 416) for a communications network having a first integrated circuit (IC) (141, 244, 344, 444) including one or more...
US-7,196,917 PFC pre-regulator frequency dithering circuit
A circuit and method of dithering the switching frequency of an off-line power factor corrected (PFC) pre-regulator. The circuitry used to dither the frequency...
US-7,196,890 Electrostatic discharge protection power rail clamp with feedback-enhanced triggering and conditioning circuitry
Electrostatic discharge protection circuitry includes a timing circuit operably coupled between the high supply side and low supply side of an associated...
US-7,196,887 PMOS electrostatic discharge (ESD) protection device
A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A...
US-7,196,740 Projection TV with improved micromirror array
In order to minimize light diffraction along the direction of switching and more particularly light diffraction into the acceptance cone of the collection...
US-7,196,684 Spatial light modulator with charge-pump pixel cell
A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the...
US-7,196,643 Resolver arrangement
A resolver arrangement that is inexpensive and yet offers high resolution and high noise rejection includes a carrier signal generator and two processing...
US-7,196,640 Relaxation oscillator based keypad decoder
The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC...
US-7,196,585 Fast-response current limiting
An amplifier (10'') has a first amplifier stage (14) for producing a control current (I.sub.X) in response to an input voltage. A second amplifier stage (16) has...
US-7,196,581 Amplifier switching control circuit and method for current shunt instrumentation amplifier having extended...
An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a generally parallel configuration, each with inputs coupled through...
US-7,196,564 High frequency balanced phase interpolator
A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase...
US-7,196,398 Resistor integration structure and technique for noise elimination
A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate...
US-7,196,338 Ultra-thin sample preparation for transmission electron microscopy
In accordance with the invention, there is a method of fabricating a material for transmission electron microscopy comprising removing a first portion from a...
US-7,196,309 Photodetection circuit
In a photo detection arrangement, the current through a detector 10 is sensed by a series resistor Rs and amplified and amplified at 21. The output of the...
US-7,195,984 Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit...
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively...
US-7,195,965 Premature breakdown in submicron device geometries
The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502,...
US-7,195,954 Low capacitance coupling wire bonded semiconductor device
A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a...
US-7,195,679 Versatile system for wafer edge remediation
The present invention provides a system (200, 300) for remediating aberrations along the perimeter of a semiconductor wafer (202). The system includes a cleaning...
US-7,195,479 Hot liner insertion/removal fixture
A fixture (30) adapted to permit the heated exchange of a liner (14) from an operating vertical furnace (10). The fixture is adapted to secure to the base of the...
US-7,194,646 Real-time thermal management for computers
A real-time thermal management apparatus and method for a computer employs a monitor (40) to determine whether a CPU may rest based upon real-time sampling of...
US-7,194,169 Notched adjustable aperture
An adjustable aperture system includes a stationary aperture operable to remove a portion of a lower intensity light communicated through a light bundle. The...
US-7,194,024 Method for adaptive hybrid selection during ADSL modem training
The methodology accomplishes adaptive hybrid selection during ADSL modem training. The adaptive hybrid selection method maximizes performance for ADSL modems in...
US-7,193,880 Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory
Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected...
US-7,193,739 Real time fax-over-packet for broadband access gateways
The invention teaches elimination of the need for allocating a telephony port or equivalent processor resource for realtime facsimile transmission through a...
US-7,193,554 Quantizer circuit
According to an aspect of present invention, a quantizer is provided with reduced power consumption and area. Such a feature is attained by providing the input...
US-7,193,469 System and method for testing gate oxide of an amplifier
An amplifier system and method is provided for performing gate oxide integrity (GOI) testing of a power output field effect transistor (FET) of the amplifier...
US-7,193,442 USB 1.1 for USB OTG implementation
This invention enables a USB 1.1 device and a USB 1.1 host to communicate seamlessly with a USB OTG device. The invention complies with both USB 1.1 and OTG...
US-7,193,403 Current driver
A current driver that can control variation in the consumed current in conjunction with variation in the setting value of the driving current. The mirror current...
US-7,193,277 Application of different isolation schemes for logic and embedded memory
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and...
US-7,192,894 High performance CMOS transistors using PMD liner stress
A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a...
US-7,192,880 Method for line etch roughness (LER) reduction for low-k interconnect damascene trench etching
The present invention provides a method for etching a substrate 100. The method includes conducting a first etch on an anti-reflective layer 170 and a portion of...
US-7,192,877 Low-K dielectric etch process for dual-damascene structures
A method includes performing a first etch process to form a via hole in a dual-damascene integrated circuit structure comprising a first dielectric layer and a...
US-7,192,863 Method of eliminating etch ridges in a dual damascene process
A dual damascene process employs a via fill material (38) with an etch rate that is within 60% of an etch rate that an underlying dielectric layer (34) etches...
US-7,192,861 Wire bonding for thin semiconductor package
An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact...
US-7,192,838 Method of producing complementary SiGe bipolar transistors
Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for...
US-7,192,809 Low cost method to produce high volume lead frames
A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222)...
US-7,191,446 Method for resource management in a real-time embedded system
A method is disclosed for allocating processing resources, such as instruction execution which can be measured in MIPs or memory capacity, or other resources of...
US-7,191,445 Method using embedded real-time analysis components with corresponding real-time operating system software objects
An operating system (OS) is used in a system with a processor that includes embedded real-time analysis components. The OS includes software objects which...
US-7,191,199 Method and device for computing an absolute difference
Computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second...
US-7,191,162 FIFO interface for flag-initiated DMA frame synchro-burst operation
The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit...
US-7,191,025 Variable digital high and low pass filters
A system (10) for providing an integer number N of filters. The system comprises an input (D.sub.i) for receiving a digital audio signal and an output (D.sub.o)...
US-7,190,717 System and method for tone ordering in discrete multi-tone (DMT) modems
A system and method for reordering tones of a DMT signal within a communication system is described. Cross tone correlated noise in a received signal is...
US-7,190,665 Blind crosstalk cancellation for multicarrier modulation
Crosstalk can be cancelled in a composite communication signal (y.sub.m) which includes a primary signal component associated with communication data and which...
US-7,190,598 Three-phase low noise charge pump and method
A low noise charge pump circuit includes a first terminal of a first flying capacitor selectively coupled to a first voltage during a first recharging phase and...
US-7,190,541 Hi-speed preamplifier write driver for hard drive with improved symmetry
A write driver (38) produces balanced voltages across head (32) by using the input write data (WDX and WDY) drive transistors of a slower transistor type...
US-7,190,400 Charge multiplier with logarithmic dynamic range compression implemented in charge domain
A CCD device incorporates Charge Multiplication in its CCD registers together with charge domain Dynamic Range compression. This structure preserves the high...
US-7,190,214 Amplifier apparatus for use with a sensor
An apparatus for use with a sensor includes first and second signal treating circuit segments coupled with the sensor for presenting a substantially balanced...
US-7,189,938 Process and system to package residual quantities of wafer level packages
Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include...
US-7,189,627 Method to improve SRAM performance and stability
A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased...
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