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Patent # Description
US-9,397,211 Lateral MOSFET with buried drain extension layer
An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the...
US-9,397,182 Transistor structure with silicided source and drain extensions and process for fabrication
A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel...
US-9,397,180 Low resistance sinker contact
An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into...
US-9,397,164 Deep collector vertical bipolar transistor with enhanced gain
An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base...
US-9,397,100 Hybrid high-k first and high-k last replacement gate process
An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric...
US-9,397,085 Bi-directional ESD protection device
An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is...
US-9,397,023 Integration of heat spreader for beol thermal management
A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader...
US-9,397,009 Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer...
A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the...
US-9,396,951 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,396,948 Layer transfer of silicon onto III-nitride material for heterogenous integration
An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first...
US-9,396,144 High speed data transmission
A data reception circuit removes reliance on stacked transistors providing analog logic processing. A first trigger element outputs an up signal in response to...
US-9,395,985 Efficient central processing unit (CPU) return address and instruction cache
A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is...
US-9,395,780 USB bridge circuit gating RID.sub.--A and RID.sub.--GND for IDGND
A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus...
US-9,395,444 Mitigation of spurious signals in GNSS receivers
A method of processing received satellite signals is provided. The method includes detecting frequency, power level, code phase and doppler frequency of a...
US-9,395,413 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-9,395,412 Inverted TCK controller, update register address/select output to shift register
A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an...
US-9,395,253 Resistance and offset cancellation in a remote-junction temperature sensor
A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A...
US-9,392,662 Systems and methods of LED color overlap
The disclosed systems and methods emphasize driving LEDs in series and in parallel with the same LED driver chip and a single inductor. For creating overlap,...
US-9,391,653 Computing filtered signal as mid-value between first and second variables
Undesired variations in a signal are removed by initializing two boundaries comprising an upper boundary and a lower boundary to track the signal level. At...
US-9,391,635 Block scanner and run-level encoder from AC to DC values
A block encode circuit (800) including a scanner (820) operable to scan a block having data values spaced apart in the block by run-lengths to produce a...
US-9,391,634 Systems and methods of low power decimation filter for sigma delta ADC
Example embodiments of the systems and methods of low power decimation filter exploit the single bit data input to the filter and the symmetry of the filter...
US-9,391,627 Method and apparatus for reducing SAR input loading
The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an...
US-9,391,553 Hybrid controller for brushless DC motor
A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual...
US-9,391,160 Unguarded Schottky barrier diodes with dielectric underetch at silicide interface
One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric...
US-9,390,011 Zero cycle clock invalidate operation
A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU...
US-9,389,869 Multithreaded processor with plurality of scoreboards each issuing to plurality of pipelines
A multi-threaded microprocessor for processing instructions in single threaded mode and multithreaded modes. The microprocessor includes instruction dependency...
US-9,389,625 DC-DC converter controller apparatus with dual-counter digital integrator
DC-DC converter PWM controllers and dual counter digital integrators are presented for integrating an error between a reference voltage signal and a feedback...
US-9,386,286 Sparse source array for display pixel array illumination with rotated far field plane
A pixel array display system including an illumination source of discrete emitters with uniform emitting areas, a separate collimator in front of each emitter,...
US-9,385,790 Periodic bandwidth widening for inductive coupled communications
A method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially...
US-9,385,774 Built in self test and method for RF transceiver systems
Integrated circuit transceiver circuitry (2) includes a first resonant circuit (3A) coupled to a narrowband interface (6,7A,7B,21) between a first amplifier...
US-9,385,669 Class-E outphasing power amplifier with efficiency and output power enhancement circuits and method
An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF...
US-9,385,600 Low-loss step-up and step-down voltage converter
A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the...
US-9,385,216 Monolithically integrated active snubber
A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor,...
US-9,385,196 Fast switching IGBT with embedded emitter shorting contacts and method for making same
Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon...
US-9,385,187 High breakdown N-type buried layer
A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low...
US-9,385,140 Efficient buried oxide layer interconnect scheme
An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried...
US-9,385,117 NPN heterojunction bipolar transistor in CMOS flow
An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the...
US-9,385,044 Replacement gate process
An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer...
US-9,384,850 OTP read sensor architecture with improved reliability
Circuits and methods for reading an OTP memory cell with improved reliability. To read a first OTP memory cell, a first current amount generated by a second,...
US-9,384,826 Circuits and methods for performance optimization of SRAM memory
In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in...
US-9,384,726 Feedback microphones encoder modulators, signal generators, mixers, amplifiers, summing nodes
A noise-cancelling system includes headset for generating a feedback signal for noise-cancellation in response to sound externally generated from the headset....
US-9,384,109 Processor with debug pipeline
A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution...
US-9,384,003 Determining whether a branch instruction is predicted based on a capture range of a second instruction
An electronic processor is provided for use with a memory (2530) having selectable memory areas. The processor includes a memory area selection circuit (MMU)...
US-9,383,761 Apparatus and method for multiphase SMPS interleaving
In described examples, a phase interleaver obtains (i) a first signal indicating a variance between a reference voltage and a regulated output voltage and (ii)...
US-9,383,586 Stereoscopic imaging systems utilizing solid-state illumination and passive glasses
A stereoscopic display system employs narrowband illumination light beams and passive glasses with built-in interference filters. The system is also compatible...
US-9,383,418 Integrated dual axis fluxgate sensor using double deposition of magnetic material
A method of fabricating fluxgate devices to measure the magnetic field in two orthogonal, in plane directions, by using a composite-anisotropic magnetic core...
US-9,383,410 Inverted TCK access port selector having resets selecting one tap
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The...
US-9,383,403 TSVs connected to ground and combined stimulus and testing leads
This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the...
US-9,383,393 Dual-comparator circuit with dynamic VIO shift protection
A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary...
US-9,383,209 Undocking and re-docking mobile device inertial measurement unit from vehicle
According to an aspect of the present disclosure, the relative attitude between an inertial measurement unit (IMU), present on a mobile device, and the frame of...
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