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Patent # Description
US-7,170,769 High performance and reduced area architecture for a fully parallel search of a TCAM cell
A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one...
US-7,170,667 Lifetime improvement in microstructures with deformable elements
A microelectromechanical device with a plastically deformable element of is exposed to illumination light so as to elongate the lifetime of the device on the...
US-7,170,628 Efficient processing of images in printers
A printer controller in which the image data received in indexed format is stored only in indexed format. The image data is converted to long format when...
US-7,170,277 Shield for tester load boards
The invention provides tester load board shields (10, 40) for attachment to tester load boards. The shields (10, 40) of the invention protect from physical...
US-7,169,659 Method to selectively recess ETCH regions on a wafer surface using capoly as a mask
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while...
US-7,169,345 Method for integrated circuit packaging
According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool...
US-7,167,532 Method and apparatus for generating an oversampling clock signal
A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL....
US-7,167,522 Video deblocking filter
Decomposition of deblocking filters used in block-based video compression allows reduction of computational redundancies.
US-7,167,350 Design implementation to suppress latchup in voltage tolerant circuits
The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard...
US-7,167,334 Digital actuator control and method
Disclosed are methods and apparatus for digital control of a head-disk assembly actuator with dynamic velocity compensation. In preferred methods of the...
US-7,167,148 Data processing methods and apparatus in digital display systems
Data processing methods and apparatus used in digital display system transpose pixel-by-pixel data into bitplane-by-bitplane data. The methods and apparatus are...
US-7,167,143 Method and system for determining characteristics of optical signals on spatial light modulator surfaces
The present application describes a system and method for determining characteristics (e.g., exact band location, orientation and height and the spot shape and...
US-7,167,056 High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature...
The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature...
US-7,167,038 Power efficiency control output buffer
A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the...
US-7,167,017 Isolation cell used as an interface from a circuit portion operable in a power-down mode to a circuit portion...
An isolation cell provided between a first module (which can operate in either a power-up mode or a power down mode) and a second module. According to an aspect...
US-7,166,903 Drain extended MOS transistors with multiple capacitors and methods of fabrication
Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate...
US-7,166,858 Variable capacitor single-electron device
The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a...
US-7,166,546 Planarization for integrated circuits
A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In...
US-7,166,481 Method for evaluating and modifying solder attach design for integrated circuit packaging assembly
A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment...
US-7,165,847 Method and system for light processing using a gold segment
A method for generating images includes shining a beam of light through a filter wheel to produce filtered light. The filter wheel includes red, green, and blue...
US-7,165,711 Substrate alignment method and apparatus
A substrate that is not lying flat on its substrate tray can present significant process problems when a vacuum pickup attempts to pick up the substrate and...
US-7,165,028 Method of speech recognition resistant to convolutive distortion and additive distortion
A speech recognizer operating in both ambient noise (additive distortion) and microphone changes (convolutive distortion) is provided. For each utterance to be...
US-7,165,018 Address range comparator for detection of multi size memory accesses with data matching qualification and full...
An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators...
US-7,164,886 Bluetooth transparent bridge
System and method for transparently attaching wireless peripherals to a computer using a Bluetooth wireless network. A preferred embodiment comprises an...
US-7,164,704 Beam forming for transmit using bluetooth modified hopping sequences (BFTBMH)
A communication circuit (28) is designed with a signal processing circuit (370) arranged to produce a first plurality of data signals and receive a second...
US-7,164,596 SRAM cell with column select line
An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to...
US-7,164,483 Optimal approach to perform raster operations
Raster operations (ROPs) are executed using a few core blocks which implement the logical operations (e.g., AND, OR, XOR) forming the basis for the raster...
US-7,164,397 Discrete light color processor
Methods and apparatus for use with a discrete bit display system such as a DLP.RTM. display system for increasing brightness by using secondary light bits (such...
US-7,164,291 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors
System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a...
US-7,164,199 Device packages with low stress assembly process
A microelectromechanical device package and a low-stress inducing method for packaging a microelectromechanical device are disclosed in this invention. The...
US-7,164,186 Structure of semiconductor device with sinker contact region
A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a...
US-7,164,174 Single poly-emitter PNP using dwell diffusion in a BiCMOS technology
A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is...
US-7,164,160 Integrated circuit device with a vertical JFET
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
US-7,163,880 Gate stack and gate stack etch sequence for metal gate integration
The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes...
US-7,163,878 Ultra-shallow arsenic junction formation in silicon germanium
In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method...
US-7,163,877 Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing
A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer...
US-7,163,838 Method and apparatus for forming a DMD window frame with molded glass
An improved method for fabricating a window frame/window piece assembly is disclosed in this application. A window frame having an opening in its inner portion...
US-7,162,684 Efficient encoder for low-density-parity-check codes
Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix...
US-7,162,652 Integrated circuit dynamic parameter management in response to dynamic energy evaluation
A power management system (12) in an electronic device (10). The system comprises circuitry (14.sub.x), responsive to at least one system parameter, for...
US-7,162,618 Method for enhancing the visibility of effective address computation in pipelined architectures
The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective...
US-7,162,586 Synchronizing stack storage
A system comprises a main stack, a local data stack and plurality of flags. The main stack comprises a plurality of entries and is located outside a processor's...
US-7,162,552 Programmable extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least...
US-7,162,411 Dynamic data trace output scheme
Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO....
US-7,162,159 Position demodulation through polarization of the transmitted beam in an optical wireless link
A method of eliminating the non-linearities associated with the remote feedback sensor, such as a quad position detector, used in a micro-electro-mechanical...
US-7,161,978 Transmit and receive window synchronization
A system for synchronizing sender sliding windows and receiver sliding windows employed in wireless packet communication is provided. The sender sliding window...
US-7,161,941 Wireless packet communications with extended addressing capability
In packet communications, one existing address code in a predetermined address field (AM_ADDR) of a packet can be used to indicate that bits in another field...
US-7,161,690 Method for enhancing rendering of picture elements
For a given lookup table, maximum and minimum values of index values are determined. The lookup table is expanded in both directions by replicating the lowest...
US-7,161,608 Digital system and method for displaying images using shifted bit-weights for neutral density filtering...
Disclosed herein are visual display systems and methods capable of having shifted bit-weights in neutral density filtering (NDF) applications. In one embodiment,...
US-7,161,521 Multi-stage analog to digital converter architecture
According to an aspect of the present invention, different reference voltage levels are used for different stages of a multi-stage analog to digital converter...
US-7,160,782 Method of manufacture for a trench isolation structure having an implanted buffer layer
The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the...
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