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Patent # Description
US-7,160,650 Method of inspecting a mask
The invention relates to a method of inspecting a mask comprising the steps: patterning a semiconductor material with a reference mask, patterning the...
US-7,159,138 Method and apparatus for data transfer between at least two modules interconnected by a serial data bus
Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data...
US-7,159,083 Programmable transition state machine
The programmable transition state machine of this invention is designed to allow implementation of hardware capable of increasing the performance of critical...
US-7,159,002 Biquad digital filter operating at maximum efficiency
An architecture for a biquad (70), second-order infinite impulse response (IIR) digital filter, that is capable of operating at maximum efficiency, is disclosed....
US-7,158,904 System and method for correcting an inaccurate clock
System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock...
US-7,158,902 Process parameter based I/O timing programmability using electrical fuse elements
Electrical fuses (eFuses) are applied to the task of achieving very tightly controlled Input-Output (I/O) timing specifications. The I/O timing is made...
US-7,158,727 10 Gbit/sec transmit structure with programmable clock delays
The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and...
US-7,158,690 Enhancing the resolution of measurement systems employing image capturing systems to measure lengths
Two scales having unequal pitches are used to measure lengths with a greater resolution than that offered by an image capturing system operating alone. In an...
US-7,158,684 Entropy coding scheme for video coding
A method of variable length coding classifies each received symbol into one of a plurality of classifications having a corresponding variable length code table...
US-7,158,600 Charge pump phase locked loop
A phase lock loop circuit 60 has a phase frequency detector 62, a charge pump 64, an active filter 87 and a voltage-controlled oscillator 100. The phase detector...
US-7,158,455 Servo error detecting device for optical disk
Servo error signal circuitry apparatus and methods are described. The difference between two bottom envelope signals SEbtm and SFbtm is calculated by a...
US-7,158,402 Asymmetric static random access memory device having reduced bit line leakage
An SRAM device comprising a column having opposing bit lines, asymmetric memory cells spanning the opposing bit lines in alternating orientations, and a sense...
US-7,158,279 Spatial light modulators with non-uniform pixels
A micromirror array comprises micromirrors of different properties for use particularly in display systems. Micromirrors of different properties can be arranged...
US-7,158,180 System and method for varying exposure time for different parts of a field of view while acquiring an image
A system and method for exposing different parts of a single field of view for various and differing lengths of time while capturing an image is provided. For...
US-7,157,962 Charge pump output device with leakage cancellation
The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the...
US-7,157,945 Window comparator and method of providing a window comparator function
A window comparator comprising a single comparator circuit that has a positive input, a differential negative input, and an output, wherein limits of a window...
US-7,157,943 Frequency selection of switch mode power converters via softstart voltage level
A switch mode power converter that limits the in-rush current at start-up and reduces the occurrence of output voltage overshoot over a range of switching...
US-7,157,939 Quad state memory with converter feedback, transmission, and clock circuitry
Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring...
US-7,157,784 Drain extended MOS transistors with multiple capacitors and methods of fabrication
Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate...
US-7,157,386 Photoresist application over hydrophobic surfaces
A method of forming a layer of photoresist 28 over a surface 30 of a semiconductor wafer 10 by forming a layer of pre-wet solvent 52 over the surface 30 and...
US-7,157,363 Method for producing a semiconductor package, with a rerouted electrode formed on a resin projection portion
An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is...
US-7,157,358 Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a...
The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor...
US-7,155,687 Methods and apparatus for scan insertion
In accordance with the present electronic design automation (EDA) for integrated circuits invention prior to synthesis, dummy elements are added to the library...
US-7,155,650 IC with separate scan paths and shift states
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to...
US-7,155,646 Tap and test controller with separate enable inputs
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these...
US-7,155,637 Method and apparatus for testing embedded memory on devices with multiple processor cores
The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip....
US-7,155,617 Methods and systems for performing dynamic power management via frequency and voltage scaling
Methods and systems are provided for dynamically managing the power consumption of a digital system. These methods and systems broadly provide for varying the...
US-7,155,553 PCI express to PCI translation bridge
A PCI Express to PCI bridge enables upstream and downstream isochronous data transfer by modifying the PCI bus arbiter so that the PCI device on the PCI bus is...
US-7,155,548 Sequential device control with time-out function
This invention is used in a real time system that includes a host processor, interface hardware and an external device controlled by the interface hardware. To...
US-7,155,472 Fixed-point quantizer for video coding
A quantizer employs a scaled integral inverse ratio division for quantization of an input T by a quantization step Q. The quantizer forms an integral...
US-7,155,179 Full duplex transceiver having a method for immunizing itself against self-jamming
A full-duplex transceiver using a method immunizing itself against self-jamming. The transceiver includes a receiver and a transmitter. The receiver includes a...
US-7,154,958 Code division multiple access wireless system with time reversed space time block transmitter diversity
A wireless communication network (10) includes a wireless transmitter having a plurality of antennas (AT1.sub.1, AT1.sub.2). The transmitter includes for each of...
US-7,154,725 Hard disk drive (HDD) electrical over voltage stress (EOS) systems and methods
The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the...
US-7,154,693 Programmable overshoot for a servo writer
A HDD write driver circuit (10) having a boost current overshoot programmed by a plurality of pull-up devices (MP35, MP36, MP39, MP45). The pull-up strength of...
US-7,154,660 Testing of spatial light modulators (SLM)
System and method for correlation testing of SLMs using stroboscopic methods. A preferred embodiment comprises providing a test pattern to the SLM, configuring a...
US-7,154,557 Joint pre-/post-processing approach for chrominance mis-alignment
This invention corrects chrominance misalignment that occurs during chrominance down-sampling and up-sampling. The invention extracts a binary index from the...
US-7,154,345 PLL circuit having reduced capacitor size
A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC...
US-7,154,166 Low profile ball-grid array package for high power
A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface...
US-7,154,047 Via structure of packages for high frequency semiconductor devices
A substrate (300) for a package of high frequency semiconductor devices comprising a planar insulating substrate having a plurality of parallel, planar metal...
US-7,153,782 Effective solution and process to wet-etch metal-alloy films in semiconductor processing
A solution and method is described for etching TaN, TiN, Cu, FSG, TEOS, and SiN on a silicon substrate in silicon device processing. The solution is formed by...
US-7,153,756 Bonded SOI with buried interconnect to handle or device wafer
A method of fabricating an electrically conductive via and an SOI structure and the structure. A substrate and a device wafer are provided and an electrically...
US-7,153,711 Method for improving a drive current for semiconductor devices on a wafer-by-wafer basis
The present invention provides a method for manufacturing semiconductor devices, a method for manufacturing an integrated circuit, and a method for improving a...
US-7,153,706 Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor
The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory...
US-7,153,443 Microelectromechanical structure and a method for making the same
A microstructure and the method for making the same are disclosed herein. The microstructure has structural members, at least one of which comprises an...
US-7,152,800 Preamplifier system having programmable resistance
A biasing scheme is disclosed that helps reduce current noise in an associated device, such as, for example, a magneto-resistive device. The biasing scheme...
US-7,152,308 Wirebonder to bond an IC chip to a substrate
Thick film bond surfaces (8) on a support structure (10), such as a ceramic substrate or an IC package substrate, tend to deform during processing. A personality...
US-7,152,187 Low-power SRAM E-fuse repair methodology
A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse...
US-7,152,028 Software development tool with embedded cache analysis
This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it,...
US-7,152,025 Noise identification in a communication system
A method is provided to automatically identify noise events in a channel of a communication system comprising the steps of: receiving an input signal from the...
US-7,151,628 Micromirror array device and a method for making the same
The spatial light modulator of the present invention comprises an array of micromirrors, each of which has a reflective deflectable mirror plate. A set of posts...
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