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Patent # Description
US-7,218,604 Orthogonal frequency division multiplexing system with differing control parameters corresponding to different...
A wireless transmitter (TX.sub.1). The transmitter comprises circuitry for providing a plurality of control (CONTROL) bits and circuitry for providing a...
US-7,218,439 Apparatus and method for adjusting the resonant frequency of an oscillating device
A method for increasing the resonant frequency of a torsional hinged device having a reduced attaching area between the torsional hinges and the supporting...
US-7,218,350 Image sensor with digital output and inherent pixel non-uniformity suppression
The image sensing device provides a digital output for each pixel. As charge builds up in a pixel, the pixel output increases until it reaches a reference level....
US-7,218,132 System and method for accurate negative bias temperature instability characterization
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal...
US-7,218,029 Adjustable compensation of a piezo drive amplifier depending on mode and number of elements driven
An integrated circuit (42) provides drive signals to a piezo element (48) of a milli-actuator device (20) in a mass data storage device (10). The integrated...
US-7,217,656 Structure and method for bond pads of copper-metallized integrated circuits
A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The...
US-7,217,626 Transistor fabrication methods using dual sidewall spacers
Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure...
US-7,217,322 Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an...
A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped...
US-7,216,990 Integrated lamp and aperture alignment method and system
According to one embodiment a method for aligning a light source includes providing a lamp and a lamp interface. The lamp interface has an alignment aperture...
US-7,216,794 Bond capillary design for ribbon wire bonding
A device (100) and method (200) for bonding a ribbon wire (104) to a workpiece (106) comprising feeding the ribbon wire through a passageway (116) of an...
US-7,216,310 Design method and system for optimum performance in integrated circuits that use power management
The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic...
US-7,216,272 Method for reducing SRAM test time by applying power-up state knowledge
Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic...
US-7,216,247 Methods and systems to reduce data skew in FIFOs
The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a...
US-7,215,888 System and method of implementing variable loop gain in an optical wireless link based on distance
A system and method of varying the control loop gain of an optical wireless communication link between a transmitting station and a receiving station as an...
US-7,215,670 Hardware acceleration for reassembly of message packets in a universal serial bus peripheral device
A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB...
US-7,215,458 Deflection mechanisms in micromirror devices
A method and apparatus for operating spatial light modulator have been disclosed herein. The spatial light modulator comprises an array of micromirror devices,...
US-7,215,271 Method and apparatus for forming transient response characteristics
Transient response generating circuit A has a first circuit 3 that generates transient response OUT1 in a first polarity direction, a second circuit 4 that...
US-7,215,202 Programmable gain amplifier and method
One embodiment of the present invention may include a programmable gain amplifier comprising an input multiplexer operative to sequentially select input signals...
US-7,215,201 Integrated circuit having a low power, gain-enhanced, low noise amplifying circuit
An amplifying circuit includes an n-type transistor having a source, a gate coupled to a first bias voltage, and a drain coupled to a first supply voltage...
US-7,215,185 Threshold voltage extraction for producing a ramp signal with reduced process sensitivity
A system for providing a threshold voltage (V.sub.T) includes a V.sub.T extractor that extracts the V.sub.T for a MOS transistor relative to a first voltage...
US-7,215,000 Selectively encased surface metal structures in a semiconductor device
The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105)...
US-7,214,609 Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity...
US-7,214,607 Compliant wirebond pedestal
A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906)....
US-7,214,550 Method to produce thin film resistor using dry etch
A method of fabricating a thin film resistor (100). The resistor material (104), e.g., NiCr, is deposited. A hard mask material (106), e.g., TiW, may be...
US-7,213,184 Testing of modules operating with different characteristics of control signals using scan based techniques
Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules...
US-7,213,171 IEEE 1149.1 tap instruction scan with augmented TLM scan mode
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test...
US-7,212,931 Electric energy meter for an AC mains supply
An energy consumption meter having a variable phase error compensator. While the variable phase error compensator may provide fixed phase error compensation for...
US-7,212,607 X-ray confocal defect detection systems and methods
An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a...
US-7,212,387 Electrostatic discharge protection device including precharge reduction
ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge...
US-7,212,359 Color rendering of illumination light in display systems
A method and a color rendering filter for compensating for deficiency in illumination light from a light source in display systems are provided. The color...
US-7,212,139 System for suppressing aliasing interferers in decimating and sub-sampling systems
A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is...
US-7,212,059 Level shift circuit
The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are...
US-7,212,023 System and method for accurate negative bias temperature instability characterization
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal...
US-7,211,842 System with meshed power and signal buses on cell array
A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a...
US-7,211,516 Nickel silicide including indium and a method of manufacture therefor
The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same....
US-7,211,481 Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer
The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while...
US-7,210,078 Error bit method and circuitry for oscillation-based characterization
A method for evaluating an output of a sequential circuit 2 by storing a series of output pulses from the sequential circuit 2 and determining whether the output...
US-7,210,072 Apparatus and method for trace stream identification of a pipeline flattener primary code flush following...
When a PROGRAM CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The...
US-7,209,513 Phase, frequency and gain characterization and mitigation in SCDMA burst receiver using multi-pass processing
A method and apparatus provide phase, frequency and gain characterization and mitigation in a synchronized code division multiple access (SCDMA) burst receiver...
US-7,209,467 Adaptive adjustment of backoff times in wireless network communications
A wireless network, including a plurality of network elements such as a wireless access point (9), and computer stations (2, 4, 6), is disclosed. The wireless...
US-7,209,060 Reducing variation in reference voltage when the load varies dynamically
Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference...
US-7,209,058 Trace receiver data compression
A method repacks variable width trace data into a different packet length previous to being stored into memory. In order to conserve bandwidth, the trace data...
US-7,209,005 Class-AB amplifier for dual voltage supplies
An amplifier providing a drive signal indicative of a data input signal to a capacitive and/or resistive type load, the amplifier having a first transistor...
US-7,208,993 Input current leakage correction for multi-channel LVDS front multiplexed repeaters
A high-speed front-multiplexed multi-channel LVDS-compatible repeater circuit that limits input leakage current levels in the event one or more input voltages of...
US-7,208,409 Integrated circuit metal silicide method
Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing...
US-7,208,398 Metal-halogen physical vapor deposition for semiconductor device defect reduction
The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by...
US-7,208,388 Thin film resistor head structure and method for reducing head resistivity variance
A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce...
US-7,208,386 Drain extended MOS transistor with improved breakdown robustness
A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures...
US-7,208,380 Interface improvement by stress application during oxide growth through use of backside films
The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a...
US-7,208,379 Pitch multiplication process
A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the...
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