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Patent # Description
US-7,154,345 PLL circuit having reduced capacitor size
A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC...
US-7,154,166 Low profile ball-grid array package for high power
A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface...
US-7,154,047 Via structure of packages for high frequency semiconductor devices
A substrate (300) for a package of high frequency semiconductor devices comprising a planar insulating substrate having a plurality of parallel, planar metal...
US-7,153,782 Effective solution and process to wet-etch metal-alloy films in semiconductor processing
A solution and method is described for etching TaN, TiN, Cu, FSG, TEOS, and SiN on a silicon substrate in silicon device processing. The solution is formed by...
US-7,153,756 Bonded SOI with buried interconnect to handle or device wafer
A method of fabricating an electrically conductive via and an SOI structure and the structure. A substrate and a device wafer are provided and an electrically...
US-7,153,711 Method for improving a drive current for semiconductor devices on a wafer-by-wafer basis
The present invention provides a method for manufacturing semiconductor devices, a method for manufacturing an integrated circuit, and a method for improving a...
US-7,153,706 Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor
The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory...
US-7,153,443 Microelectromechanical structure and a method for making the same
A microstructure and the method for making the same are disclosed herein. The microstructure has structural members, at least one of which comprises an...
US-7,152,800 Preamplifier system having programmable resistance
A biasing scheme is disclosed that helps reduce current noise in an associated device, such as, for example, a magneto-resistive device. The biasing scheme...
US-7,152,308 Wirebonder to bond an IC chip to a substrate
Thick film bond surfaces (8) on a support structure (10), such as a ceramic substrate or an IC package substrate, tend to deform during processing. A personality...
US-7,152,187 Low-power SRAM E-fuse repair methodology
A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse...
US-7,152,028 Software development tool with embedded cache analysis
This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it,...
US-7,152,025 Noise identification in a communication system
A method is provided to automatically identify noise events in a channel of a communication system comprising the steps of: receiving an input signal from the...
US-7,151,628 Micromirror array device and a method for making the same
The spatial light modulator of the present invention comprises an array of micromirrors, each of which has a reflective deflectable mirror plate. A set of posts...
US-7,151,473 Digital detection of blockers for wireless receiver
A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase...
US-7,151,414 Method and circuit for frequency synthesis using a low drift current controlled oscillator with wide output...
A method and circuit for frequency synthesis using a low drift current controlled oscillator configured to provide a wide output frequency and high accuracy are...
US-7,151,409 Programmable low noise amplifier and method
A programmable gain low noise amplifier includes a tail current transistor (Q3) having a source coupled to a first reference voltage (VDD) and a drain coupled to...
US-7,151,406 Compensation of nonlinearity introduced by dead time in switching output stage
A method of operating a class D amplifier output stage that compensates for nonlinearity introduced by a residual load current during the dead time in the...
US-7,151,361 Current sensing circuitry for DC-DC converters
An inductor based DC-DC converter of the present invention employs two power switches such that only a fraction of inductor current flows through sensing...
US-7,151,309 Apparatus for improved power distribution in wirebond semiconductor packages
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and...
US-7,149,636 Method and apparatus for non-obtrusive power profiling
Systems and methods for improved power profiling of embedded applications are presented. These inventions provide the ability to unobtrusively measure the power...
US-7,149,427 Cooperating array of micromirror devices for wireless optical communication
A micromirror array assembly (10, 20) for use in optical modules (5, 17) in a wireless network system is disclosed. The micromirror array assembly (10, 20)...
US-7,149,253 Wireless communication
A frequency division multiplexing wireless transmission on two or more antennas with the set of symbols on subcarriers of a burst transmitted by one antenna...
US-7,149,240 Method of and apparatus for controlling system timing with use of a master timer
A digital transceiver operative for direct sequence spread spectrum communications is described, a master counter associated with a zero offset pseudorandom...
US-7,149,137 Process monitoring for ferroelectric memory devices with in-line retention test
The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising...
US-7,149,027 Digital micromirror device with simplified drive electronics for use as temporal light modulator
A digital micromirror device (DMD) modified for use as a temporal light modulator. The DMD is modified so that the mirrors of the DMD have a preferential tilt...
US-7,148,716 System and method for the probing of a wafer
According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set...
US-7,148,558 Versatile system for limiting mobile charge ingress in SOI semiconductor structures
Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the...
US-7,148,546 MOS transistor gates with doped silicide and methods for making the same
Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and...
US-7,148,143 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor
The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor...
US-7,148,140 Partial plate anneal plate process for deposition of conductive fill material
A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more...
US-7,148,121 Semiconductor on insulator device architecture and method of construction
An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14...
US-7,148,097 Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors
A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate...
US-7,148,085 Gold spot plated leadframes for semiconductor devices and method of fabrication
A leadframe for use with integrated circuit chips comprising a plated layer of gold selectively covering areas of said leadframe intended for solder attachment;...
US-7,147,447 Plastic semiconductor package having improved control of dimensions
A device with a semiconductor chip (801) assembled on a planar substrate (802) and encapsulation compound (810) surrounding the assembled chip and a portion of...
US-7,146,613 JAVA DSP acceleration by byte-code optimization
A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing ...
US-7,146,518 Filter circuit with automatic adjustment of cutoff frequency via average signal values
A low-pass filter in a read channel, having an adjustable cutoff frequency has a low-pass filter 14, a time measuring circuit 15, a storage computing circuit 19...
US-7,146,284 Method of testing phase lock loop status during a Serializer/Deserializer internal loopback built-in self-test
System and method are implemented to allow phase lock loop (PLL) status testing during a Serializer/Deserializer (SERDES) internal loopback built-in self-test...
US-7,145,884 Speaker tracking on a single core in a packet based conferencing system
A distributed conferencing system having a plurality of conferencing nodes to connect groups of participants to a conference. Each of the conferencing nodes...
US-7,145,831 Data synchronization arrangement
A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock...
US-7,145,822 Method and apparatus for optimal write restore for memory
According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit...
US-7,145,789 Low power low area precharge technique for a content addressable memory
A technique to pre-charge a CAM block array including a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a...
US-7,145,573 Method and system to combine a digital graphics object and a digital picture
Combining a graphics object with a picture where only the luminance value of a graphics object pixel is written to a corresponding picture pixel if the...
US-7,145,399 Type-II all-digital phase-locked loop (PLL)
System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop...
US-7,145,354 Resilient probes for electrical testing
An apparatus for electrical testing having probes (201) constructed of metal elements (201a) of about equal size bonded together in substantially linear...
US-7,145,204 Guardwall structures for ESD protection
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to...
US-7,144,808 Integration flow to prevent delamination from copper
The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an...
US-7,144,802 Vapor deposition of benzotriazole (BTA) for protecting copper interconnects
A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized...
US-7,144,789 Method of fabricating complementary bipolar transistors with SiGe base regions
In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the...
US-7,144,780 Semiconductor device and its manufacturing method
The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown...
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