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Patent # Description
US-7,123,057 Self-biased comparator with hysteresis control for power supply monitoring and method
A voltage monitor circuit for biasing a well region of a CMOS circuit includes a self-biased comparator which compares first (INP) and second (INN) input...
US-7,122,895 Stud-cone bump for probe tips used in known good die carriers
A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an...
US-7,122,862 Reduction of channel hot carrier effects in transistor devices
A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a...
US-7,122,466 Two step semiconductor manufacturing process for copper interconnects
An embodiment of the invention is a method of manufacturing copper interconnects 30 on a semiconductor wafer 10 where an electroplating process is used to...
US-7,122,442 Method and system for dopant containment
According to one embodiment, a semiconductor device is provided. The semiconductor device includes an oxide layer. The semiconductor device also includes a...
US-7,122,435 Methods, systems and structures for forming improved transistors
A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to...
US-7,122,413 Method to manufacture silicon quantum islands and single-electron devices
The present invention provides a method of manufacturing a single-electron transistor device (100). The method includes forming a thinned region (110) in a...
US-7,120,854 Wireless access modem having downstream channel resynchronization method
A resynchronization method for use in a data communication system having a first device configured to transmit data at a symbol rate to a second device. The...
US-7,120,843 IC with scan distributor and scan collector circuitry
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing...
US-7,120,842 Mechanism to enhance observability of integrated circuit failures during burn-in tests
A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are...
US-7,120,771 Secure mode for processors supporting MMU
A digital system is provided with a secure mode (3.sup.rd level of privilege) built in a non-invasive way on a processor system that includes a processor core,...
US-7,120,715 Priority arbitration based on current task and MMU
A digital system and method of operation is provided in which several processors (740(0) 740(n)) are connected to a shared resource (750). Each processor has an...
US-7,120,546 Integrated spectrum analyzer for tuners
A scheme to provide a spectral view of the signals present at the customer premises equipment by the network operator and includes a digital signal processor...
US-7,120,468 System and method for steering directional antenna for wireless communications
A system and method for determining an optimal antenna position of a directional antenna in a wireless communication system are described. The optimal antenna...
US-7,120,213 Using SISO decoder feedback to produce symbol probabilities for use in wireless communications that utilize...
An apparatus and method for transmitting and receiving a bit stream. On the transmission side, coded bits (Y.sub.t) and an interleaved version of the coded bits...
US-7,120,186 Methods and apparatus for use in generating data sequences for spread spectrum communications
Methods and apparatus for use in generating data sequences for direct sequence spread spectrum (DSSS) communications are described. One exemplary method includes...
US-7,120,082 System for reducing row periphery power consumption in memory devices
The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation....
US-7,119,999 Pre-regulator with reverse current blocking
An apparatus includes a blocking N-channel MOS (LDMOS) transistor that prevents current flow when the supply connection is reversed. When connected properly, the...
US-7,119,940 Capacitively coupled micromirror
A capacitively coupled microelectromechanical device and method of operation. The micromechanical device comprises: a semiconductor substrate; a member operable...
US-7,119,847 Method for identifying format of a received video signal
A method for identifying format of a video signal including a raster-synchronizing signal having a timing signal spanning a synch interval and a synch-follower...
US-7,119,845 Image resizing system and method
Image resizing through resampling by poly-phase filtering with a phase generation from input parameters but with lower resolution of the phase for filter...
US-7,119,723 Decoding variable length codes while using optimal resources
In one aspect, code-words of variable lengths are decoded using a multi-stage decoding approach, with different stages being of different sizes (and thus...
US-7,119,601 Backgate pull-up for PMOS pass-gates
The pass-gate circuit with backgate pull-up includes: a pass-gate transistor coupled between a first port and a second port; a backgate pull-up transistor...
US-7,119,498 Current control device for driving LED devices
A current control device for driving LED devices uses a switched-mode current control loop inside of an output intensity low-frequency pulse width modulation...
US-7,119,444 Versatile system for charge dissipation in the formation of semiconductor device structures
The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200),...
US-7,119,386 Versatile system for triple-gated transistors with engineered corners
The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate...
US-7,119,006 Via formation for damascene metal conductors in an integrated circuit
A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is...
US-7,118,981 Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated...
In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a...
US-7,118,980 Solid phase epitaxy recrystallization by laser annealing
Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial...
US-7,118,979 Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate...
The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated...
US-7,118,977 System and method for improved dopant profiles in CMOS transistors
According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a...
US-7,118,959 Integrated circuit capacitor having antireflective dielectric
A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom...
US-7,118,958 Method of manufacturing a metal-insulator-metal capacitor using an etchback process
The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a...
US-7,118,925 Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step
A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of...
US-7,118,226 Sequential color recapture for image display systems
A method for transmitting light in an image display system includes generating a beam of light from a light source. The beam of light is directed at a first...
US-7,118,225 Illumination system
The addition of DMD illumination modulator(s) 702 in series with projection SLM(s) 706/709 to produce high-performance projection displays with improved optical...
US-7,117,800 Overhead material handling system and track block
A material handling system (100) and method (200) for isolating a carrier mechanism (110) from the system. The system (100) comprises a track (103) having a...
US-7,117,799 Overhead material handling system and track block
The present invention is directed to a material handling system (100) and method (200) for isolating a carrier mechanism (110) from the system. The system (100)...
US-7,117,476 Determining feasibility of IC edits
A computer method of analyzing an integrated circuit ("IC") masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer...
US-7,117,427 Reduced complexity decoding for trellis coded modulation
The present application describes a method of implementing a Viterbi algorithm (VA) for trellis coded modulation (TCM) decoding in communication equipment....
US-7,117,398 Program counter range comparator with equality, greater than, less than and non-equal detection modes
An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators...
US-7,116,699 Frequency re-mapping for structure adaptive frequency hopping
The invention generally provides a method of intelligent frequency hopping such as in Bluetooth and Home RF networks. The method (400) includes the acts of...
US-7,116,459 Field diode detection of excess light conditions for spatial light modulator
An improved SLM that is capable of detecting when light incident on the SLM exceeds a predetermined threshold. A diode is fabricated around, or within the pixel...
US-7,116,261 Method and apparatus for accurate inverse-linear voltage/current generator
To make use of its full input voltage operating range, an analog-to-digital converter is configured with a switched-capacitor circuit to produce a digital output...
US-7,116,239 Current sense components failure detection in a multi-phase power system
An evaluator (210) having an input (207) for receiving a signal indicative of a channel current sensed via a sensor in a mutlichannel current sharing system, and...
US-7,116,172 High-swing folded cascode having a novel gain-boost amplifier
A circuit topology for gain boosted high-swing folded cascode has been improved to maximize the available dynamic range in applications having low supply voltage...
US-7,116,169 Driver apparatus and method of operation thereof
A driver apparatus comprising a signal switching circuit coupled for receiving an actuation signal and generating a first and a second control signal in response...
US-7,116,158 Bandgap reference circuit for ultra-low current applications
A bandgap reference circuit as may be used in ultra-low current applications is provided. An exemplary bandgap circuit can be configured to generate a positive...
US-7,116,139 Apparatus and method for controlling operation of a processor device during startup
An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage...
US-7,116,113 Systems and methods for sense FET calibration
Systems, methods and circuits for sense circuit calibration. In one particular case, a system is provided that includes a sense circuit, a calibration circuit,...
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