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Patent # Description
US-7,151,309 Apparatus for improved power distribution in wirebond semiconductor packages
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and...
US-7,149,636 Method and apparatus for non-obtrusive power profiling
Systems and methods for improved power profiling of embedded applications are presented. These inventions provide the ability to unobtrusively measure the power...
US-7,149,427 Cooperating array of micromirror devices for wireless optical communication
A micromirror array assembly (10, 20) for use in optical modules (5, 17) in a wireless network system is disclosed. The micromirror array assembly (10, 20)...
US-7,149,253 Wireless communication
A frequency division multiplexing wireless transmission on two or more antennas with the set of symbols on subcarriers of a burst transmitted by one antenna...
US-7,149,240 Method of and apparatus for controlling system timing with use of a master timer
A digital transceiver operative for direct sequence spread spectrum communications is described, a master counter associated with a zero offset pseudorandom...
US-7,149,137 Process monitoring for ferroelectric memory devices with in-line retention test
The present invention facilitates evaluation of ferroelectric memory devices. A ferroelectric memory device is fabricated that comprises memory cells comprising...
US-7,149,027 Digital micromirror device with simplified drive electronics for use as temporal light modulator
A digital micromirror device (DMD) modified for use as a temporal light modulator. The DMD is modified so that the mirrors of the DMD have a preferential tilt...
US-7,148,716 System and method for the probing of a wafer
According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set...
US-7,148,558 Versatile system for limiting mobile charge ingress in SOI semiconductor structures
Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the...
US-7,148,546 MOS transistor gates with doped silicide and methods for making the same
Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and...
US-7,148,143 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor
The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor...
US-7,148,140 Partial plate anneal plate process for deposition of conductive fill material
A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more...
US-7,148,121 Semiconductor on insulator device architecture and method of construction
An SOI architecture is provided that comprises an inner substrate 10 which has a buried conductor layer 12 formed on an outer surface thereof. A bonding layer 14...
US-7,148,097 Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors
A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate...
US-7,148,085 Gold spot plated leadframes for semiconductor devices and method of fabrication
A leadframe for use with integrated circuit chips comprising a plated layer of gold selectively covering areas of said leadframe intended for solder attachment;...
US-7,147,447 Plastic semiconductor package having improved control of dimensions
A device with a semiconductor chip (801) assembled on a planar substrate (802) and encapsulation compound (810) surrounding the assembled chip and a portion of...
US-7,146,613 JAVA DSP acceleration by byte-code optimization
A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing ...
US-7,146,518 Filter circuit with automatic adjustment of cutoff frequency via average signal values
A low-pass filter in a read channel, having an adjustable cutoff frequency has a low-pass filter 14, a time measuring circuit 15, a storage computing circuit 19...
US-7,146,284 Method of testing phase lock loop status during a Serializer/Deserializer internal loopback built-in self-test
System and method are implemented to allow phase lock loop (PLL) status testing during a Serializer/Deserializer (SERDES) internal loopback built-in self-test...
US-7,145,884 Speaker tracking on a single core in a packet based conferencing system
A distributed conferencing system having a plurality of conferencing nodes to connect groups of participants to a conference. Each of the conferencing nodes...
US-7,145,831 Data synchronization arrangement
A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock...
US-7,145,822 Method and apparatus for optimal write restore for memory
According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit...
US-7,145,789 Low power low area precharge technique for a content addressable memory
A technique to pre-charge a CAM block array including a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a...
US-7,145,573 Method and system to combine a digital graphics object and a digital picture
Combining a graphics object with a picture where only the luminance value of a graphics object pixel is written to a corresponding picture pixel if the...
US-7,145,399 Type-II all-digital phase-locked loop (PLL)
System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop...
US-7,145,354 Resilient probes for electrical testing
An apparatus for electrical testing having probes (201) constructed of metal elements (201a) of about equal size bonded together in substantially linear...
US-7,145,204 Guardwall structures for ESD protection
A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor (510) in a first n-well (511) having its source connected to...
US-7,144,808 Integration flow to prevent delamination from copper
The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an...
US-7,144,802 Vapor deposition of benzotriazole (BTA) for protecting copper interconnects
A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized...
US-7,144,789 Method of fabricating complementary bipolar transistors with SiGe base regions
In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the...
US-7,144,780 Semiconductor device and its manufacturing method
The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown...
US-7,143,660 Method and system for processing semiconductor wafers
A method for processing semiconductor wafers includes processing a semiconductor wafer in a processing chamber having upper and lower chambers, decoupling the...
US-7,142,891 Device bound flashing/booting for cloning prevention
A method comprising downloading a boot image onto a mobile communication device and generating a device-bound certificate ("DBC"). The DBC preferably comprises...
US-7,142,841 Telephone personal information manager
A personal information manager (PIM) has been provided for use in controlling telephone call message responses for a wireless communications network mobile...
US-7,142,605 Method to transfer data without a clock or strobe signal
A method of communicating a data bit between memory devices is disclosed, having the steps of: indicating a first value of the data bit by transitioning, between...
US-7,142,466 Determining optimal time instances to sense the output of a memory array which can generate data outputs with...
A tracking circuit in a memory unit which generates sense enable signals at optimal time instances. The tracking circuit includes a scalable driver block...
US-7,142,156 System and method for providing time to a satellite positioning system (SPS) receiver from a networked time server
System and method for enabling signal acquisition in a satellite positioning system (SPS) when signals from SPS satellites are attenuated by the operating...
US-7,142,050 Recovery from clipping events in a class D amplifier
A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20),...
US-7,142,019 System and method for reducing power-on transient current magnitude
System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch...
US-7,141,480 Tri-gate low power device and method for manufacturing the same
The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first...
US-7,141,468 Application of different isolation schemes for logic and embedded memory
The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and...
US-7,141,455 Method to manufacture LDMOS transistors with improved threshold voltage control
A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie...
US-7,140,016 Media accelerator quality of service
Integration of DSP running algorithms with general purpose processor running applications including plugin objects as proxies for the DSP algorithms and with...
US-7,139,988 Modeling metastability in circuit design
A computer program (100, 200) encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to...
US-7,139,959 Layered low density parity check decoding for digital communications
A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit (38) is disclosed....
US-7,139,854 Pipelining access to serialization tokens on a bus
Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a...
US-7,139,700 Hybrid speech coding and system
Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of...
US-7,139,320 Method and apparatus for multicarrier channel estimation and synchronization using pilot sequences
Method and apparatus for OFDM synchronization and channel estimation. In a temporal embodiment, received embedded system pilot symbols are inverse Fourier...
US-7,139,229 Optical disk identification circuit
The present invention offers an optical disk determination circuit that can improve the stability of the operation to detect the peak (pulse signal) of the...
US-7,139,113 Digital micro-mirror device with free standing spring tips and distributed address electrodes
According to one embodiment of the present invention a micro-mirror element comprises a first address portion, a second address portion, and one or more address...
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