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Patent # Description
US-7,173,340 Daisy chaining of serial I/O interface on stacking devices
A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding...
US-7,173,296 Reduced hydrogen sidewall spacer oxide
An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD...
US-7,172,936 Method to selectively strain NMOS devices using a cap poly layer
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of...
US-7,171,577 Methods and apparatus for a system clock divider
A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively...
US-7,171,497 Progressive extended compression mask for dynamic trace
This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least...
US-7,171,435 Circuits, systems, and methods implementing approximations for logarithm, inverse logarithm, and reciprocal
A digital signal system (30) for determining an approximate logarithm of a value of x having a base b is described. The system comprises circuitry for storing x...
US-7,171,335 System and method for the analysis of semiconductor test data
According to one embodiment, a method of analyzing semiconductor test data includes receiving a plurality of raw data entries from a testing system. Each raw...
US-7,171,068 Method to improve an extinction ratio of an optical device
A method to improve an extinction ratio of an optical device, the method includes positioning at least a majority of a plurality of micro-mirrors in an off-state...
US-7,171,035 Alignment mark for e-beam inspection of a semiconductor wafer
An alignment mark to be used in conjunction with e-beam imaging to identify specific feature locations on a chip including a unique "L" shaped pattern of...
US-7,170,962 Data transmission
A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each...
US-7,170,937 Complexity-scalable intra-frame prediction technique
This invention is a method of encoding intra frames when encoding a motion picture. A set of intra frame prediction modes includes a low-complexity subset. A...
US-7,170,927 Methods and apparatus for an ADSL transceiver
An ADSL transceiver hybrid circuit uses one or more isolated couplers (optical couplers, capacitors, or the like) configured to minimize the transmit signal...
US-7,170,861 Distributed device identifier numbering and total device counting algorithm with smart time division...
A distributed method and apparatus for assigning a unique identifier number to devices connected in a sequential fashion and determining a total device count is...
US-7,170,828 Removable face plate compressed digital music player
This invention comprises a two part audio system in which all of the processing power is allocated to a small, lightweight satellite part that is the face unit....
US-7,170,769 High performance and reduced area architecture for a fully parallel search of a TCAM cell
A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one...
US-7,170,667 Lifetime improvement in microstructures with deformable elements
A microelectromechanical device with a plastically deformable element of is exposed to illumination light so as to elongate the lifetime of the device on the...
US-7,170,628 Efficient processing of images in printers
A printer controller in which the image data received in indexed format is stored only in indexed format. The image data is converted to long format when...
US-7,170,277 Shield for tester load boards
The invention provides tester load board shields (10, 40) for attachment to tester load boards. The shields (10, 40) of the invention protect from physical...
US-7,169,659 Method to selectively recess ETCH regions on a wafer surface using capoly as a mask
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while...
US-7,169,345 Method for integrated circuit packaging
According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool...
US-7,167,532 Method and apparatus for generating an oversampling clock signal
A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL....
US-7,167,522 Video deblocking filter
Decomposition of deblocking filters used in block-based video compression allows reduction of computational redundancies.
US-7,167,350 Design implementation to suppress latchup in voltage tolerant circuits
The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard...
US-7,167,334 Digital actuator control and method
Disclosed are methods and apparatus for digital control of a head-disk assembly actuator with dynamic velocity compensation. In preferred methods of the...
US-7,167,148 Data processing methods and apparatus in digital display systems
Data processing methods and apparatus used in digital display system transpose pixel-by-pixel data into bitplane-by-bitplane data. The methods and apparatus are...
US-7,167,143 Method and system for determining characteristics of optical signals on spatial light modulator surfaces
The present application describes a system and method for determining characteristics (e.g., exact band location, orientation and height and the spot shape and...
US-7,167,056 High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature...
The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature...
US-7,167,038 Power efficiency control output buffer
A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the...
US-7,167,017 Isolation cell used as an interface from a circuit portion operable in a power-down mode to a circuit portion...
An isolation cell provided between a first module (which can operate in either a power-up mode or a power down mode) and a second module. According to an aspect...
US-7,166,903 Drain extended MOS transistors with multiple capacitors and methods of fabrication
Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate...
US-7,166,858 Variable capacitor single-electron device
The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a...
US-7,166,546 Planarization for integrated circuits
A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In...
US-7,166,481 Method for evaluating and modifying solder attach design for integrated circuit packaging assembly
A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment...
US-7,165,847 Method and system for light processing using a gold segment
A method for generating images includes shining a beam of light through a filter wheel to produce filtered light. The filter wheel includes red, green, and blue...
US-7,165,711 Substrate alignment method and apparatus
A substrate that is not lying flat on its substrate tray can present significant process problems when a vacuum pickup attempts to pick up the substrate and...
US-7,165,028 Method of speech recognition resistant to convolutive distortion and additive distortion
A speech recognizer operating in both ambient noise (additive distortion) and microphone changes (convolutive distortion) is provided. For each utterance to be...
US-7,165,018 Address range comparator for detection of multi size memory accesses with data matching qualification and full...
An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators...
US-7,164,886 Bluetooth transparent bridge
System and method for transparently attaching wireless peripherals to a computer using a Bluetooth wireless network. A preferred embodiment comprises an...
US-7,164,704 Beam forming for transmit using bluetooth modified hopping sequences (BFTBMH)
A communication circuit (28) is designed with a signal processing circuit (370) arranged to produce a first plurality of data signals and receive a second...
US-7,164,596 SRAM cell with column select line
An array of SRAM cells (e.g., 6T single-ended or 8T differential cells) and method is discussed having variable high and low voltage power supplies to provide to...
US-7,164,483 Optimal approach to perform raster operations
Raster operations (ROPs) are executed using a few core blocks which implement the logical operations (e.g., AND, OR, XOR) forming the basis for the raster...
US-7,164,397 Discrete light color processor
Methods and apparatus for use with a discrete bit display system such as a DLP.RTM. display system for increasing brightness by using secondary light bits (such...
US-7,164,291 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors
System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a...
US-7,164,199 Device packages with low stress assembly process
A microelectromechanical device package and a low-stress inducing method for packaging a microelectromechanical device are disclosed in this invention. The...
US-7,164,186 Structure of semiconductor device with sinker contact region
A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a...
US-7,164,174 Single poly-emitter PNP using dwell diffusion in a BiCMOS technology
A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is...
US-7,164,160 Integrated circuit device with a vertical JFET
We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It...
US-7,163,880 Gate stack and gate stack etch sequence for metal gate integration
The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes...
US-7,163,878 Ultra-shallow arsenic junction formation in silicon germanium
In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method...
US-7,163,877 Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing
A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer...
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