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Patent # Description
US-7,113,044 Precision current mirror and method for voltage to current conversion in low voltage applications
A voltage-to-current conversion circuit includes an error amplifier (12A) which amplifies a voltage difference between the drains of the first (6) and second (7)...
US-7,113,039 Gain-boosted opamp with capacitor bridge connection
The number of compensation capacitors of an opamp may be reduced by connecting the compensation/decoupling capacitor element or elements between the load node...
US-7,112,953 Method for detecting epitaxial (EPI) induced buried layer shifts in semiconductor devices
The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried...
US-7,112,950 Integrated circuit for use with an external hall sensor, and hall sensor module
An integrated circuit for use with an external Hall sensor that permits to at least substantially cancel out the temperature drifts of the Hall sensor, as caused...
US-7,112,546 Method of manufacturing semiconductor devices comprising a deposition tool cleaning process having a moving...
The present invention provides, in one embodiment, a method of manufacturing semiconductor devices. The method comprises transferring one or more substrate into...
US-7,112,540 Pretreatment for an electroplating process and an electroplating process in including the pretreatment
The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other...
US-7,112,532 Process for forming a dual damascene structure
The invention describes a method for forming a dual damascene structure. An etch stop layer (150) is formed on a dielectric layer (140). A second dielectric...
US-7,112,516 Fabrication of abrupt ultra-shallow junctions
One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity...
US-7,112,497 Multi-layer reducible sidewall process
The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design...
US-7,112,480 Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices
A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively...
US-7,112,288 Methods for inspection sample preparation
Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected...
US-7,112,286 Thin film resistor structure and method of fabricating a thin film resistor structure
A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical...
US-7,111,292 Apparatus and method for secure program upgrade
An appliance includes a memory having at least a hidden partition of memory. The hidden partition of memory operates to store at least a portion of a program...
US-7,111,182 Thread scheduling mechanisms for processor resource power management
A real-time operating system runs on a processor and dynamically manages the power state of individual circuits or resources with the processor. Thus, if a...
US-7,111,177 System and method for executing tasks according to a selected scenario in response to probabilistic power...
A distributed processing system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power...
US-7,110,956 Capability predictor
A capability predictor that comprises a database 15 of capability of multiple designs is disclosed. The process capability data includes costs, quality, cycle...
US-7,110,782 Cell search synchronization
Cell search synchronization in spread spectrum communications systems using primary and second synchronization codes with symbol partitioning for shorter...
US-7,110,732 Subsampling RF receiver architecture
A subsampling receiver (50, 50', 50'') for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50', 50'') may be implemented into a...
US-7,110,477 Gaussian frequency shift keying digital demodulator
A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after...
US-7,110,445 Oversampled clip-shaping
The present invention provides an apparatus, system and method of peak-to-average reduction of an oversampled signal for a digital communication system. Peak...
US-7,110,432 Orthogonal chirp modulation in multipath environments
Methods and systems for communication systems are disclosed. Chirp signals generated according to a chirp rate and carrier frequency are used for communication....
US-7,110,370 Method and apparatus for coordinating multi-point to point communications in a multi-tone data transmission system
A variety of bidirectional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a...
US-7,110,204 Process-insensitive write current generation for a HDD preamplifier writer equipped with parallel output...
The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel...
US-7,109,902 Method and system for sampling a signal
According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal...
US-7,109,838 System for integrating a toroidal inductor in a semiconductor device
An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a...
US-7,109,812 Apparatus and method for presenting a linear capacitive output in response to a voltage input
An apparatus for presenting a substantially linear capacitive output at at least one output locus in response to a voltage input at an input locus, the voltage...
US-7,109,802 Bipolar differential to single ended transfer circuit with gain boost
A differential to single-ended signal transfer circuit that allows increased gain and improved AC performance while reducing power supply voltage requirements....
US-7,109,738 Method for modeling inductive effects on circuit performance
A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) and three reference...
US-7,109,697 Temperature-independent amplifier offset trim circuit
An operational amplifier having temperature-compensated offset correction. The amplifier includes an operational amplifier circuit, that has a first input field...
US-7,109,556 Method to improve drive current by increasing the effective area of an electrode
The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100...
US-7,109,077 Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound
A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the...
US-7,107,848 Active scan velocity control for torsional hinged MEMS scanner
System and method for adjusting an operational parameter of a component that drifts with temperature changes. The system includes a torsional hinged device that...
US-7,107,300 Circuits, systems, and methods implementing approximations for inverse logarithm
A digital signal system (50) determines an approximate antilog x from a value of f(x), where x has a base b.
US-7,107,175 Continuous digital background calibration in pipelined ADC architecture
Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital...
US-7,107,072 Interface module for a portable telephone that facilitates direct portable telephone/portable computer coupling
The present invention provides a solution to the dual problems of mobility and portability associated with using a portable telephone in combination with a...
US-7,106,567 Hard disk drive (HDD) electrical over voltage stress (EOS) systems and methods
The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the...
US-7,106,492 Bias voltage routing scheme for a digital micro-mirror device
An apparatus for use with a digital micro-mirror includes a hinge disposed outwardly from a substrate and capable of at least partially supporting a micro-mirror...
US-7,106,491 Split beam micromirror
A system and method of providing a micromirror pixel 400 that is highly resistant to bright failure states. The micromirror 400 uses an asymmetric yoke 402 to...
US-7,106,097 IC with dual input output memory buffer
An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal thereof, which signal...
US-7,105,923 Device and method for including passive components in a chip scale package
The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a...
US-7,105,891 Gate structure and method
CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.
US-7,104,434 Screen printing squeegee for applying solder paste
Apparatus and methods for applying solder paste to circuits, such as integrated circuits, are disclosed. The apparatus and methods comprise a squeegee blade...
US-7,103,883 System and method for translating include files
An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source...
US-7,103,547 Implementing a high accuracy continuous speech recognizer on a fixed-point processor
A small vocabulary speech recognizer suitable for implementation on a 16-bit fixed-point DSP is described. The input speech xt is sampled at analog-to-digital...
US-7,103,489 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space
When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss...
US-7,103,095 Spread spectrum code correlator
Spread spectrum receiver with correlating coprocessor having common datapath for received signal correlations and code cross-correlations for efficient...
US-7,103,085 Wireless communications system with secondary synchronization code based on values in primary synchronization code
A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting...
US-7,102,844 Dual direction integrator for constant velocity control for an actuator using sampled back EMF control
A controller providing increased control with lesser final error for an actuator when there is a force accelerating the actuator, such as at the end of travel...
US-7,102,440 High output current wideband output stage/buffer amplifier
A high output current wideband output stage/buffer amplifier that has reduced quiescent current requirements. The output stage/buffer amplifier includes a...
US-7,102,341 Apparatus for controlling a power factor correction converter device
An apparatus for controlling output signals at an output locus of a power converting device has a rectifier coupled to receive an input signal and present a...
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