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Integrated dual axis fluxgate sensor using double deposition of magnetic
A method of fabricating fluxgate devices to measure the magnetic field in two orthogonal, in plane directions, by using a composite-anisotropic magnetic core...
Inverted TCK access port selector having resets selecting one tap
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The...
TSVs connected to ground and combined stimulus and testing leads
This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the...
Dual-comparator circuit with dynamic VIO shift protection
A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary...
Undocking and re-docking mobile device inertial measurement unit from
According to an aspect of the present disclosure, the relative attitude between an inertial measurement unit (IMU), present on a mobile device, and the frame of...
Packing insert for disc-shaped objects
A packing insert for disc-shaped objects comprising a ring and a deformable contacting portion supported by the ring and extending from a circumference of the...
Pixel retrieval for frame reconstruction
A video decoder receives data representing an encoded image frame partitioned into one or more partitions. The video decoder stores the motion vector associated...
Sample adaptive offset (SAO) parameter signaling
Techniques for signaling of sample adaptive offset (SAO) information that may reduce the coding rate for signaling such information in the compressed bit stream...
Multichannel video port interface using no external memory
This invention is a video line encapsulation protocol which allows multiple low definition video streams to be combined into a single super frame of high...
Enhanced carrier sense multiple access (CSMA) protocols
Power Line Communications (PLC) device for enhanced carrier sense multiple access (CSMA) protocols are described. The PLC device includes a modem, an AC...
System for transmitting information between circuits
A system for transferring information from a first circuit to a second circuit includes first and second isolation elements coupled between the first circuit...
Phase detection in power line communication systems
Phase detection between service nodes in a as "PRIME" ("PoweRline Intelligent Metering Evolution") communications network, in which the service nodes are...
Isolation circuits for digital communications and methods to provide
isolation for digital communications
Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes...
Controllable circuits, processes and systems for functional ESD tolerance
An electronic circuit (100) includes a first circuit (140) having an output and operable to give a warning but that has a sensitivity to an electrostatic...
Well resistors and polysilicon resistors
An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled...
Method of making a QFN package
A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and...
Process for forming driver for normally on III-nitride transistors to get
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode...
Packaging a semiconductor device having wires with polymerized insulator
A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with...
Method of fabricating an electronic circuit
Circuits and methods of fabricating circuits are disclosed herein. A method of fabricating an electronic circuit includes placing an electronic component on a...
Methods and devices for determining logical to physical mapping on an
Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes...
Transform and quantization architecture for video coding and decoding
A method of encoding a video stream in a video encoder is provided that includes computing an offset into a transform matrix based on a transform block size,...
WiFi USB protocol
A wireless universal serial bus (USB) system that includes a wireless USB host, a first wireless USB device, and a second wireless USB device. The wireless USB...
Core wrapper link instruction register controls responsive to select
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing...
Network coexistence through active superframe interleaving
Embodiments of the invention provide coexistence among independent networks through active superframe interleaving. Network hubs and devices exchange signals...
Kalman filter iteratively performing time/measurement update of
user/relative floor locations
Several systems and methods for location estimation in a multi-floor environment are disclosed. In an embodiment, the method includes performing wireless...
Mode estimation in pipelined architectures
A video system includes an encoder for generating a compressed bit stream in response to a received video signal. The encoder includes a mode decision processor...
Frame structure for medium access in body area networks (BAN)
A system and method for providing a variety of medium access and power management methods are disclosed. A defined frame structure allows a hub and a node to...
Capture selection for digital pre-distortion adaptation and capture
concatenation for frequency hopping...
A digital pre-distortion component includes: a first capturing component that captures a first sample set of data; a first generating component that generates a...
Micro-step resistance networks
A series-structure, parallel-structure and combined structure of micro-step resistance network circuits is disclosed. Micro-step resistance is maintained, while...
Circuits and methods for constant output current in a flyback converter
Flyback converters are disclosed herein. An embodiment of a flyback converter includes a transformer having a primary side and a secondary side. A switch is...
Dielectric waveguide with RJ45 connector
A communication cable includes a dielectric wave guide (DWG) that has a dielectric core member that has a first dielectric constant value and a cladding...
Bipolar transistor including lateral suppression diode
A transistor includes an emitter of a first conductivity type, base of a second conductivity type, collector of the first conductivity type, and cathode of a...
Semiconductor package having etched foil capacitor integrated into
A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and...
Integrating multi-output power converters having vertically stacked
An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first...
Flat no-lead packages with electroplated edges
A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad,...
High perfomance DMA controller for video processors
This invention for a VDMA will enable ultra HD resolution (4K) encode/decode at 30 frames per second. This invention maximizes interconnect/DDR utilization and...
Deadlock-avoiding coherent system on chip interconnect
This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked...
Coherent cache system with optional acknowledgement for out-of-order
coherence transaction completion
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a...
Optimum cache access scheme for multi endpoint atomic access in a
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
Method and apparatus for multiplying binary operands
Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer...
Electronic device and method for generating a curvature compensated
bandgap reference voltage
The invention relates to an electronic device with a bandgap reference generator including a first path with series connection of a first bipolar transistor, a...
Substrate with state machine circuitry and tap state monitor circuitry
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced...
PSD/PSC serial scan path having first and second strobe inputs
Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these...
Method and apparatus for SSIM-based bit allocation
A method and an encoder for SSIM-based bits allocation. The encoder includes a memory and a processor utilized for allocating bits based on SSIM, wherein the...
Communication reception with compensation for relative variation between
transmit bit interval and receiver...
The effect of timing inaccuracy is compensated for in a communication receiver that receives a transmission of bits temporally separated by a bit interval. The...
Differentiator based spread spectrum modulator
A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to...
Adjustable and buffered reference for ADC resolution and accuracy
An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference...
Leading-edge phase-cut dimmer detector
Circuits and methods for detecting the presence of a leading-edge phase-cut dimmer. The dimmer detector comprises an edge detector, a pulse stretcher and a...
Interleaved forward converter with wide input and output dynamic range
An interleaved forward voltage converter having a first inverter stage has a first transformer having a first secondary winding coupled to a filter inductor. A...
Phase current balancing for multiphase converters
A DC-DC converter includes a first differential voltage sensor to detect a first inductor current by sensing a first differential voltage across a first power...