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Patent # Description
US-9,407,318 Interference mitigation detector encompassing high power peak integer chip value
A receiver (100) is provided for signals of different signal strengths and modulated with respective pseudorandom noise (PN) codes. The receiver (100) includes...
US-9,407,250 Systems for accurate multiplexing
The disclosure presented herein provides example embodiments of systems for accurate multiplexing. The systems and methods presented may be suitable for...
US-9,407,249 System and method for pulse width modulation
A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has...
US-9,406,779 Spacer shaper formation with conformal dielectric film for void free PMD gap fill
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer...
US-9,406,774 Field effect transistor and method of making
A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the...
US-9,406,769 Silicide formation due to improved SiGe faceting
An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the...
US-9,406,621 Ultraviolet energy shield for non-volatile charge storage memory
An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing....
US-9,405,637 Locking/unlocking CPUs to operate in safety mode or performance mode without rebooting
An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to...
US-9,405,089 High-temperature isotropic plasma etching process to prevent electrical shorts
A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an...
US-9,405,064 Microstrip line of different widths, ground planes of different distances
An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and...
US-9,404,973 Test clock/test mode slect (TCK/TMS), select, data register (DR) connection circuitry between test access port...
An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a...
US-9,404,727 Inductive position sensing with single channel interface to multiple resonant sensors
An inductive sensing system includes multiple resonant sensors interfaced to an inductance-to-digital conversion (IDC) unit through a single channel interface....
US-9,402,248 Method for determining the location of control channels in the uplink of communication systems
Embodiments of the invention provide methods for user equipments to implicitly determine the location for the transmission of uplink control signaling...
US-9,401,803 Flexible scrambler/descrambler architecture for a transceiver
An apparatus is provided. A polynomial register having a plurality of bits is provided, where the polynomial register is configured to store a user-defined...
US-9,401,748 Method and apparatus for channel state information feedback in a coordinated multi-point communication system
A method of operating a wireless communication system (FIG. 4) is disclosed. The method includes receiving a plurality of reference signals from a respective...
US-9,401,722 Autoconfigurable phase-locked loop which automatically maintains a constant damping factor and adjusts the loop...
A phase-locked loop (PLL) includes a state machine programmed to automatically produce a set of control signals to select a charge-pump current and integrating...
US-9,401,702 Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate...
Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock...
US-9,401,638 System and method for single phase transition for multiphase DCDC converters
A DCDC converter includes a controller, an up/down counter, a first power stage and a second power stage. The controller generates an up/down control signal....
US-9,401,410 Poly sandwich for deep trench fill
A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon...
US-9,401,365 Epitaxial source/drain differential spacers
A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over...
US-9,401,196 Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data
Read-only ("RO") data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as...
US-9,400,296 Tracking energy consumption using a boost-buck technique
The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least...
US-9,398,300 Method, system and apparatus for intra-prediction in video signal processing using combinable blocks
A method, apparatus and system for a video encoder for selecting a block of intermediate size from a set of block sizes for intra-prediction estimation for...
US-9,398,223 Shared-field image projection and capture system
According to one embodiment of the present invention a method for capturing images on a screen is disclosed. The method includes directing light from a surface...
US-9,397,824 Gear shifting from binary phase detector to PAM phase detector in CDR architecture
A device and method for providing clock data recovery (CDR) in a receiver is disclosed. The method comprises receiving a Phase Amplitude Modulation (PAM)...
US-9,397,816 Partial CQI feedback in wireless networks
Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an...
US-9,397,693 Asynchronous analog-to-digital converter
An asynchronous analog-to-digital converter (AADC) and a method of using the AADC are shown. The AADC includes a digital-to analog-converter (DAC), a...
US-9,397,688 Hybrid digital-to-analog conversion system
A digital-to-analog conversion (DAC) circuit has a resistor ladder circuit controlled by high order bits and a resistor string circuit controlled by low order...
US-9,397,685 Sensor with low power model based feature extractor
Described examples include low power analog front end circuits for sensing repeating signal waveforms, including a first sampling circuit to sample an input...
US-9,397,667 Shared divide by N clock divider
A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division...
US-9,397,597 Sensed motor winding current adapting blanking period between max/min values
Stepper motor winding current regulation methods and apparatus adapt a maximum blanking period to generate an adapted blanking period that is proportional to a...
US-9,397,594 BLDC motor sinusoidal PWM with single phase BEMF slot detection
A back electromotive force (BEMF) zero cross may be detected in a brushless direct current (BLDC) motor that is controlled by pulse width modulation (PWM). A...
US-9,397,564 DC-DC switching regulator with transconductance boosting
A switching regulator comprising a droop amplifier responsive to a reference voltage and a feedback voltage to generate a droop voltage. The droop amplifier...
US-9,397,211 Lateral MOSFET with buried drain extension layer
An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the...
US-9,397,182 Transistor structure with silicided source and drain extensions and process for fabrication
A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel...
US-9,397,180 Low resistance sinker contact
An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into...
US-9,397,164 Deep collector vertical bipolar transistor with enhanced gain
An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base...
US-9,397,100 Hybrid high-k first and high-k last replacement gate process
An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric...
US-9,397,085 Bi-directional ESD protection device
An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is...
US-9,397,023 Integration of heat spreader for beol thermal management
A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader...
US-9,397,009 Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer...
A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the...
US-9,396,951 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,396,948 Layer transfer of silicon onto III-nitride material for heterogenous integration
An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first...
US-9,396,144 High speed data transmission
A data reception circuit removes reliance on stacked transistors providing analog logic processing. A first trigger element outputs an up signal in response to...
US-9,395,985 Efficient central processing unit (CPU) return address and instruction cache
A processor includes an instruction fetch unit and an instruction decode unit. The instruction fetch unit includes an instruction pre-fetch buffer and is...
US-9,395,780 USB bridge circuit gating RID.sub.--A and RID.sub.--GND for IDGND
A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus...
US-9,395,444 Mitigation of spurious signals in GNSS receivers
A method of processing received satellite signals is provided. The method includes detecting frequency, power level, code phase and doppler frequency of a...
US-9,395,413 Blocking the effects of scan chain testing upon a change in scan chain topology
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain...
US-9,395,412 Inverted TCK controller, update register address/select output to shift register
A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an...
US-9,395,253 Resistance and offset cancellation in a remote-junction temperature sensor
A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A...
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