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Patent # Description
US-7,098,094 NiSi metal gate stacks using a boron-trap
A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity...
US-7,097,110 Temperature compensation systems and methods for use with read/write heads in magnetic storage devices
Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic...
US-7,096,649 Method and apparatus for integrated circuit storage tube retention pin removal and insertion
While the manufacturing of integrated circuits (IC) has become a mostly automated process, the loading of the ICs into storage and shipping tubes 105 still...
US-7,096,471 Apparatus for resource management in a real-time embedded system
An apparatus is disclosed for allocating processing resources, such as instruction execution which can be measured in MIPs or memory capacity, or other resources...
US-7,096,308 LPC transaction bridging across a PCI.sub.--express docking connection
A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station....
US-7,096,301 Communications interface for enabling extension of an internal common bus architecture (CBA)
A serial communications interface is described that enables the extension of an internal Communications Bus Architecture (CBA) bus segment to one or more...
US-7,096,141 System and method for testing a device
In a method and system for testing a device, a tester is operable to generate a first set of test signals for testing the device. The tester is electrically...
US-7,095,987 Method and apparatus for received uplinked-signal based adaptive downlink diversity within a communication system
A first downlink transmission beam and a second downlink transmission beam is determined based on a received user-derived signal. The first downlink transmission...
US-7,095,819 Direct modulation architecture for amplitude and phase modulated signals in multi-mode signal transmission
Multiple-mode direct phase/amplitude modulation circuitry (20) for use in a transceiver (17) of a device such as a wireless handset (10) is disclosed. The...
US-7,095,671 Electrical fuse control of memory slowdown
Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional...
US-7,095,594 Active read/write head circuit with interface circuit
A method and apparatus for collocating an interface circuit with a disk drive read/write head is described. In one embodiment the interface circuit is attached...
US-7,095,494 Method and apparatus for measuring temporal response characteristics of digital mirror devices
A method and system for measuring the temporal response of a micromirror array to a variety of driving signals. A micromirror array is illuminated with a...
US-7,095,356 Providing reference voltage with desired accuracy in a short duration to a dynamically varying load
Simplifying the design of buffer amplifier circuits to provide reference voltages of desired characteristics on a path. Two separate circuits may be used to...
US-7,095,121 Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices
An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a...
US-7,095,105 Vertically stacked semiconductor device
A semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate with one or more metal standoffs providing a fixed...
US-7,094,650 Gate electrode for FinFET device
In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs....
US-7,092,827 Edge placement accuracy of signals generated by test equipment
A software controlled mechanism causing a test equipment to place the edges of test signals accurately. The mechanism determines expected time of occurrence of...
US-7,092,537 Digital self-adapting graphic equalizer and method
A self-adaptive graphic equalizer operable to equalize the affects of an audio system on an audio signal includes an adaptive graphic equalizer having a...
US-7,092,276 Series feram cell array
Memory devices and memory cell groups therefor are disclosed, which comprise series connected ferroelectric (FE) memory cells accessible using a single bitline....
US-7,092,197 Rejection of power supply variations for gain error cancellation in pulse-width-modulated motor controllers
A positioning driver (32) for a voice coil motor (22) in a disk drive system (10) is disclosed. Pulse-width-modulated prestage drivers (46) are coupled to power...
US-7,092,189 Programmable output impedance for hard drive preamplifier write driver
A write driver output circuit having a programmable output impedance. A plurality of amplifiers are disposed in parallel between an input and an output of an...
US-7,091,766 Retention register for system-transparent state retention
State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1-M3; M1-M4) is used to load...
US-7,091,556 High voltage drain-extended transistor
The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a drain-extended...
US-7,091,119 Encapsulated MOS transistor gate structures and methods for making the same
Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by...
US-7,090,787 Drying getters
A zeolite and an organic binder are mixed with a solvent to form a paste (302). The paste is then cast or molded (304) into the desired shape. A portion of the...
US-7,089,447 Apparatus and method for compression based error correction procedure in a data processing system
In a data processing system in which the complete set of op-code signal groups are stored in a ROM unit, a programmable, non-volatile memory unit stores the...
US-7,089,437 Apparatus for determining power consumed by a bus of a digital signal processor using counted number of logic...
In order to measure the power consumed by a bus in a digital signal processor, each bus conductor has a lead electrically coupled thereto. The lead is coupled to...
US-7,089,183 Accumulating transformations for hierarchical linear regression HMM adaptation
A new iterative hierarchical linear regression method for generating a set of linear transforms to adapt HMM speech models to a new environment for improved...
US-7,089,004 Method and apparatus for scheduling cell search in CDMA mobile receivers
Search scheduling circuitry for use with a wireless communication device, such as a mobile telephone, includes a search time calculator, a search period...
US-7,088,791 Systems and methods for improving FFT signal-to-noise ratio by identifying stage without bit growth
Systems and methods are provided for performing signal processing on communication data utilizing scale reduced Fast Fourier Transform computations. The present...
US-7,088,785 Block level space time transmit diversity in wireless communications
Space time transmit diversity (9, 14, 17, 19) is applied at the block level to an original block of bits (12) in order to reduce the effects of fading in...
US-7,088,607 Static memory cell and SRAM device
The objective of this invention is to provide a static memory cell and an SRAM device that can improve the write margin while preventing degradation of the...
US-7,088,602 Active gate clamp circuit for self driven synchronous rectifiers
A DC-DC converter circuit includes a transformer with a resonate filter or snubber connected at a primary side and a switch for controlling operation of the...
US-7,088,486 Yokeless hidden hinge micromirror device with double binge layer
A micromirror array 110 fabricated on a semiconductor substrate 11. The array 110 is comprised of four operating layers 12, 13, 14, 15. An addressing layer 12 is...
US-7,088,274 Difference amplifier for digital-to-analog converter
An improved circuit is provided that buffers the output of a DAC while improving the bandwidth and linearity of the circuit. A DAC comprises an output signal of...
US-7,088,273 Reducing noise in switched capacitor amplifier circuit
A switched capacitor environment in which a feedback capacitor of a stage is flipped to be used as a sampling capacitor of the next stage. Due to such use of the...
US-7,088,182 Class AB output stage circuit with stable quiescent current
A class-AB output stage circuit is configured with controllable reference voltages for providing stable quiescent current. An exemplary output stage circuit...
US-7,088,177 Amplifier apparatus
An amplifier apparatus includes: (a) an integrator having an input for receiving an input signal, and integrating the input signal to present an integrated...
US-7,088,171 Charge pump with constant output current
An improved charge pump circuit that is capable of producing a constant output current. The charge pump circuit includes a controllable current source, at least...
US-7,088,149 Enhancing SNR and throughput performance of integrated circuits
Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the...
US-7,088,123 System and method for extraction of C-V characteristics of ultra-thin oxides
In one embodiment, a method for extracting C-V characteristics of ultra-thin oxides includes coupling a device under test to a testing structure, in which the...
US-7,088,070 Resonant scanning mirror driver circuit
A resonant scanning mirror driver configured to drive a micro-electro-mechanical system (MEMS) mirror to a desired deflection utilizes a PWM pattern selected...
US-7,087,518 Method of passivating and/or removing contaminants on a low-k dielectric/copper surface
One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated...
US-7,087,493 Memory with 6T small aspect ratio cells having metal.sub.--1 elements physically connected to metal.sub.--0...
A method of forming a memory circuit comprising six transistor memory cells. The memory cells comprise first and second inverters. The inverters comprise...
US-7,087,479 Method of forming integrated circuit contacts
Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is...
US-7,087,440 Monitoring of nitrided oxide gate dielectrics by determination of a wet etch
The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide...
US-7,085,977 Method and system for detecting an outlying resistance in a plurality of resistive elements
In one aspect of the invention, a semiconductor die includes a plurality of resistive elements operable to receive a voltage differential between at least two of...
US-7,085,957 Upgrading of firmware with tolerance to failures
The firmware may contain multiple application modules, which can operate independent of each other such that upgrade of one application module does not affect...
US-7,085,699 Wire bonding simulation
Embodiments of the present invention may provide ways and uses for correlating actual wire bonding machine adjustment parameters to inputs needed for FEA...
US-7,085,325 Serial interface unit with transmit monitor
In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data...
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