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Patent # Description
US-7,060,579 Increased drive current by isotropic recess etch
A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using...
US-7,060,556 Drain extended MOS transistors with multiple capacitors and methods of fabrication
Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate...
US-7,060,538 Versatile system for electrostatic discharge protection utilizing silicon controlled rectifier
The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The...
US-7,059,191 Determining defective devices which generate sound during operation
Determining whether a device is defective by analyzing the sound signals generated by the device. Digital samples are generated to represent the sound signals....
US-7,058,912 Notifying status of execution of jobs used to characterize cells in an integrated circuit
The status of execution of jobs (used to characterize cells) is notified asynchronously. As a result, the processing and network resources may be optimally used....
US-7,058,871 Circuit with expected data memory coupled to serial input lead
A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register...
US-7,058,862 Selecting different 1149.1 TAP domains from update-IR state
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for...
US-7,058,765 Processor with a split stack
Methods and apparatuses are disclosed for implementing a processor with a split stack. In some embodiments, the processor includes a main stack and a...
US-7,058,188 Configurable digital loudness compensation system and method
An audio loudness compensation system includes a level sensor receiving an audio input signal and operable to estimate a level of the audio input signal over a...
US-7,058,126 Digital graphametric equalizer
A graphametric equalizer has graphic and parametric equalization capabilities within a single non-redundant system. A translation function capability converts...
US-7,058,114 Wireless device and method
A high speed Bluetooth system with switch-to quadrature amplitude modulation allows for simple mobile devices with video data rates in applications such as...
US-7,058,074 Unified channel access for supporting quality of service (QoS) in a local area network
Contention communications often requires a station to wait an inordinate amount of time before the station is able to transmit its data successfully. In many...
US-7,057,982 Servo error detector for optical disk
A servo error detector usable in an optical disk system is provided. An envelope detecting unit (24) detects the top envelopes and bottom envelopes of RF signals...
US-7,057,540 Sigma-delta (.SIGMA..DELTA.) analog-to-digital converter (ADC) structure incorporating a direct sampling mixer
A sigma-delta analog-to-digital converter-offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a...
US-7,057,409 Method and apparatus for non-invasively testing integrated circuits
The preferred embodiments of the present invention provide non-invasive approaches of testing ICs that use photon emission from semiconductor devices to provide...
US-7,057,284 Fine pitch low-cost flip chip substrate
A package is disclosed, which includes a substrate, a solder masker, and a first aperture through the solder mask. The substrate has a surface on which metal...
US-7,056,767 Method and apparatus for flip chip device assembly by radiant heating
A flip chip semiconductor device having non-solder contact terminals is assembled by securing the chip and substrate with a rapidly thermosetting adhesive. The...
US-7,056,752 Fabricating a die with test enable circuits between embedded cores
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test...
US-7,055,212 Clean gas injector system for reactor chamber
An improvement to a Novellus HDP SPEED reactor chamber is described. An evacuation port of the Novellus SPEED Chamber is at one location in the chamber to remove...
US-7,055,136 Configurable debug system with dynamic menus
The invention relates to a software system and method for dynamically varying context sensitive menus of a software system. In this method, a menu item is added...
US-7,054,958 Apparatus and method for responding to a interruption of a packet flow to a high level data link controller in...
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal...
US-7,054,698 System for tracking operator certification of FAB equipment and processes
A software system is provided that tracks employee and contractor operation/certification of fabrication equipment and processes is provided to ensure that only...
US-7,054,393 Short and long sequence boundary detection algorithm for wireless LAN modems
A method for detecting a boundary between two sequences in a wireless local area network is presented that permits rapid detection of the boundary. The method...
US-7,054,091 Digital processor controlled method and circuit for retracting a head carriage assembly to a parked position in...
A retract circuit (40) for retracting a data transducer carriage assembly (17) of a mass data storage device (10) to a retracted position has a digital state...
US-7,053,808 Suppressing digital-to-analog converter (DAC) error
A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that...
US-7,053,465 Semiconductor varactor with reduced parasitic resistance
A semiconductor varactor with reduced parasitic resistance. A contact isolation structure (32) is formed in a well region (20). The gate contact structures (70)...
US-7,052,150 Rod integrator
An integrating rod (200) for use with a multiple segment dynamic filter, such as a spiral dichroic color wheel having three or more narrow filters adjacent to...
US-7,051,427 Integrated circuit trimming device broken die sensor
A broken trim die tool detection sensor. The lands of the tie bar die connect with the leads of the unit to form switches. The states of these switches indicate...
US-7,051,257 Means scanning scan path parts sequentially and capturing response simultaneously
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known...
US-7,051,256 Processor emulator transferring data with emulation controller continuously without interruption
An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning...
US-7,051,197 Tracing through reset
A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware...
US-7,050,768 Signal field controller, method of controlling and MIMO transmitter employing the same
For use with a multiple-input, multiple-output (MIMO) transmitter, a signal field controller, a method of controlling signal fields and a MIMO transmitter...
US-7,050,576 Double talk, NLP and comfort noise
A state machine for attenuating the transition into and out of NLP state to reduce voice clipping and to reduce echo leak in a voice over packet signal...
US-7,050,552 System and method to mitigate pots ringing interference in DSL
A system and method are disclosed to mitigate the interference on DSL due to high frequency components associated with a change in a POTS condition, such as POTS...
US-7,050,463 Automatic bit-rate detection scheme for use on SONET transceiver
An automatic bit-rate detection scheme (30) for use in SONET/SDH transceivers (12, 14) that uses only one clocking frequency (clk), is all digital, and requires...
US-7,050,402 Wireless communications with frequency band selection
A probe, listen and select (PLS) technique can be used to select from an available frequency spectrum a frequency band whose communication quality is suitable...
US-7,050,323 Ferroelectric memory
A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first...
US-7,050,211 Torsional hinged mirror assembly with central spines and perimeter ridges to reduce flexing
A torsional hinged mirror design with reduced flexing. In addition to a central spine to prevent or reduce flexing of the tips, the mirror layer also includes...
US-7,050,191 Sub-banding of display list and video buffer for page rendering in a digital signal processor
A print method converts page description data specifying a print document into pixel data. The print system includes a central processing unit, a first memory...
US-7,050,187 Real time fax-over-packet packet loss compensation
A device and method for providing real time compensation for packet loss in the transmission of facsimile data over packet networks to avoid the generation of...
US-7,049,986 Fuse link trim algorithm for minimum residual
A parameter of an integrated circuit including a first trim array and a second trim array is trimmed by measuring an initial value of the parameter, determining...
US-7,049,842 Simultaneous pin short and continuity test on IC packages
An integrated circuit functionality test determining shorts between adjacent pins of all the IC pins while simultaneously determining pin continuity in only...
US-7,049,242 Post high voltage gate dielectric pattern plasma surface treatment
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage...
US-7,047,823 Apparatus for mounting electronic module assembly in sensor
An occupant weight sensor (1) for placement between a frame (7) fixed to the chassis of a vehicle and a second frame (8) supporting a vehicle seat has a sense...
US-7,047,451 Tracing program counter addresses using native program counter format and instruction count format
A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter...
US-7,047,284 Transfer request bus node for transfer controller with hub and ports
A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer...
US-7,047,272 Rounding mechanisms in processors
An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial...
US-7,047,270 Reporting a saturated counter value
A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number....
US-7,047,268 Address generators for mapping arrays in bit reversed order
A method and apparatus to reduce the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is...
US-7,047,263 Fast-settling digital filter and method for analog-to-digital converters
A technique and circuit is provided for facilitating a faster settling time for a digital filter for use with an analog-to-digital converter. An exemplary...
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