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Patent # Description
US-7,047,178 Emulation pause and reset tracing of multiple sync points pointing to different addresses
A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified...
US-7,047,097 High performance controller for shifting resonance in micro-electro-mechanical systems (MEMS) devices
Devices being controlled electronically via physical manipulation often display a resonance. In many circumstances, the frequency range of operation is not close...
US-7,046,963 Method and apparatus of signal estimation over generalized fading channel
A methodology of signal estimation over the generalized fading channel can be applied to any parameter whose dB value is required to be estimated. The estimator...
US-7,046,306 Processing a video signal using motion estimation to separate luminance information from chrominance...
In one embodiment, a method for processing a video signal includes: (1) receiving and storing luminance and chrominance information for each pixel in a first...
US-7,046,105 System and method for threaded plunger assembly
A system and method for a plunger assembly includes a tuning slug with a bore in the stem, a tuning screw rotatably disposed in the stem, and a coupling assembly...
US-7,046,098 All-digital frequency synthesis with capacitive re-introduction of dithered tuning information
An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word...
US-7,046,069 Method to reduce inductive effects of current variations by internal clock phase shifting
Modularized clock decoupling and signal delay management is provided for the purpose of reducing simultaneous binary signal switch-induced inductive voltage...
US-7,046,044 Differential preamplifier having balanced resistor network
The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the...
US-7,045,904 Patterned plasma treatment to improve distribution of underfill material
A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the...
US-7,045,903 Integrated power circuits with distributed bonding and current flow
A semiconductor integrated circuit comprises contact pads located over active components, which are positioned to minimize the distance for power delivery...
US-7,045,456 MOS transistor gates with thin lower metal silicide and methods for making the same
Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the...
US-7,045,436 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)
A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an...
US-7,045,431 Method for integrating high-k dielectrics in transistor devices
Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers...
US-7,045,425 Bird's beak-less or STI-less OTP EPROM
The present invention facilitates semiconductor fabrication by maintaining uniform thickness of a gate oxide layer (112) during the oxide growth process of...
US-7,045,418 Semiconductor device including a dielectric layer having a gettering material located therein and a method of...
The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of...
US-7,045,410 Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI)
A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening...
US-7,044,356 Roller wire brake for wire bonding machine
While fabricating a packaged semiconductor chip, a wire is bonded on a chip contact pad using a wire bonding machine. A bond head of the wire bonding machine is...
US-7,044,304 Anti-corrosion overcoat cover tape
A flexible carrier tape system suitable for transporting and/or storing an electrical component, which has an exposed metal surface sensitive to corrosion. The...
US-7,043,705 Estimating current density parameters on signal leads of an integrated circuit
Estimating current density parameters on signal leads of an integrated circuit using computer aided design (CAD) tools. The signal leads are modeled as an...
US-7,043,428 Background noise estimation method for an improved G.729 annex B compliant voice activity detection circuit
A method of initializing an ITU Recommendation G.729 Annex B compliant voice activity detection (VAD) device is disclosed, having the steps of (1) determining a...
US-7,043,418 Synchronizing on-chip data processor trace and timing information for export
Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of...
US-7,042,833 Modem transmission over packet networks
A system for transmitting modern signals across a packet network with improved resistance to bursty network packet loss that includes a first and a second...
US-7,042,813 Shock protection for compressed audio on a CD player
A media player permits multiple compressed media files to be concurrently stored in memory interval to the media player. By concurrently buffering more than one...
US-7,042,713 Slide case with pivotable stand member for handheld computing device
A handheld computing device includes a display screen, a main housing portion, a removable case, and a stand member. The main housing retains the display screen....
US-7,042,690 Power-line, differential, isolation loss detector
In one embodiment, an integrated differential isolation loss detector is disclosed that generates a first temperature that is a function of a high side current...
US-7,042,523 Video correction system and method using logarithmic conversion
A video correction system and method are disclosed that provide video correction for an input signal. The system includes a logarithmic converter that creates a...
US-7,042,383 High speed gain amplifier and method in ADCs
An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a...
US-7,042,290 Output stage circuit for an operational amplifier
An output stage circuit is configured for enabling an output of an amplifier circuit to be pulled upwards and/or downwards to or beyond an upper power supply or...
US-7,042,250 Synchronization of clock signals in a multi-clock domain
A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module...
US-7,042,200 Switching mode power conversion with digital compensation
The present invention provides improved line and load regulation of a switching-mode power converter (300) without requiring additional capacitors (255), either...
US-7,042,070 Direct attachment of semiconductor chip to organic substrate
A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a...
US-7,042,030 High density memory array
The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers...
US-7,041,578 Method for reducing stress concentrations on a semiconductor wafer by surface laser treatment including the...
A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses...
US-7,040,238 Overhead material handling system and track block
The present invention is directed to a material handling system (100) and method (200) for isolating a carrier mechanism (110) from the system. The system (100)...
US-7,039,901 Software shared memory bus
The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software...
US-7,039,888 Modeling process for integrated circuit film resistors
A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and...
US-7,039,852 Convolutional encoding using a modified multiplier
A wireless communications device is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device...
US-7,039,823 On-chip reset circuitry and method
An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset...
US-7,039,818 Low leakage SRAM scheme
A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry...
US-7,039,795 System and method for using a two-stage multiplexing architecture for performing combinations of passing,...
A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and...
US-7,039,790 Very long instruction word microprocessor with execution packet spanning two or more fetch packets with...
A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional...
US-7,039,789 Circular addressing algorithms providing increased compatibility with one or more higher-level programming...
Logic for circular addressing providing increased compatibility with higher-level programming languages accesses a base pointer pointing to a first element of an...
US-7,039,667 4-2 compressor
A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first...
US-7,039,665 Efficient reconstruction
Efficient reconstruction of a discrete signal in a range from subband coefficients of multirate analysis filtering translates the range into required input...
US-7,039,581 Hybrid speed coding and system
Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of...
US-7,039,321 Method of controlling alignment of an optical wireless communication link
A method that allows an optical wireless communication link between transmitting and receiving stations to be established and used reliably without the need for...
US-7,039,038 Adaptive fragmentation for wireless network communications
A wireless local area network (LAN) adapter (20) that optimizes the length of message packets, for example according to the IEEE 802.11 standard, and in an...
US-7,039,036 Reduced complexity primary and secondary synchronization codes with good correlation properties for WCDMA
A circuit for processing binary sequences is designed with a plurality of stages (530 534) coupled to provide plural signal paths (526,528). Each stage includes...
US-7,039,017 System and method for detecting and locating interferers in a wireless communication system
A system and method is provided for monitoring interference in a wireless communication system. The system and method monitor error statistic data at one or more...
US-7,038,932 High reliability area efficient non-volatile configuration data storage for ferroelectric memories
Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory...
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