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Patent # Description
US-7,039,901 Software shared memory bus
The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software...
US-7,039,888 Modeling process for integrated circuit film resistors
A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and...
US-7,039,852 Convolutional encoding using a modified multiplier
A wireless communications device is disclosed, in which certain digital coding functions are realized according to a modified multiplier architecture. The device...
US-7,039,823 On-chip reset circuitry and method
An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset...
US-7,039,818 Low leakage SRAM scheme
A memory device (20) having substantially reduced leakage current in a sleep/data retention mode whereby at least a portion (25, 28) of the periphery circuitry...
US-7,039,795 System and method for using a two-stage multiplexing architecture for performing combinations of passing,...
A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and...
US-7,039,790 Very long instruction word microprocessor with execution packet spanning two or more fetch packets with...
A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional...
US-7,039,789 Circular addressing algorithms providing increased compatibility with one or more higher-level programming...
Logic for circular addressing providing increased compatibility with higher-level programming languages accesses a base pointer pointing to a first element of an...
US-7,039,667 4-2 compressor
A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first...
US-7,039,665 Efficient reconstruction
Efficient reconstruction of a discrete signal in a range from subband coefficients of multirate analysis filtering translates the range into required input...
US-7,039,581 Hybrid speed coding and system
Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of...
US-7,039,321 Method of controlling alignment of an optical wireless communication link
A method that allows an optical wireless communication link between transmitting and receiving stations to be established and used reliably without the need for...
US-7,039,038 Adaptive fragmentation for wireless network communications
A wireless local area network (LAN) adapter (20) that optimizes the length of message packets, for example according to the IEEE 802.11 standard, and in an...
US-7,039,036 Reduced complexity primary and secondary synchronization codes with good correlation properties for WCDMA
A circuit for processing binary sequences is designed with a plurality of stages (530 534) coupled to provide plural signal paths (526,528). Each stage includes...
US-7,039,017 System and method for detecting and locating interferers in a wireless communication system
A system and method is provided for monitoring interference in a wireless communication system. The system and method monitor error statistic data at one or more...
US-7,038,932 High reliability area efficient non-volatile configuration data storage for ferroelectric memories
Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory...
US-7,038,896 Solid state motor protector
A solid state motor protector has a first PTC chip (positive temperature coefficient of resistivity) electrically connected in series relation with a second...
US-7,038,715 Digital still camera with high-quality portrait mode
A digital still camera (10) receives and digitizes visible radiation (17) and sound waves (32) from a scene (12). When an operator actuates a shutter release...
US-7,038,311 Thermally enhanced semiconductor package
A thermally enhanced BGA semiconductor device 10 having a heat sink 12 formed from a single piece of material with an expanded base and a pedestal in contact...
US-7,038,258 Semiconductor device having a localized halo implant therein and method of manufacture therefor
The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an...
US-7,037,837 Method of fabricating robust nucleation/seed layers for subsequent deposition/fill of metallization layers
A method for fabricating a seed layer. A seed layer (126) is deposited over a barrier layer (124) using a three-step process comprising a low AC bias power step,...
US-7,037,823 Method to reduce silanol and improve barrier properties in low k dielectric ic interconnects
A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO.sub.2 and a first silylization...
US-7,037,799 Breakdown voltage adjustment for bipolar transistors
Devices and methods are disclosed related to a bipolar transistor device and methods of fabrication. A top region is formed at a surface of and within a base...
US-7,035,985 Method and apparatus for accessing a memory core multiple times in a single clock cycle
An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the...
US-7,035,893 4-2 Compressor
A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first...
US-7,035,756 Continuous digital background calibration in pipelined ADC architecture
Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital...
US-7,035,750 On-chip test mechanism for transceiver power amplifier and oscillator frequency
An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF...
US-7,035,546 Optical wireless multiport hub
An optical communication transmitter (13), receiver (15), and transceiver (17) having distinctive retro-reflective elements (30) and/or reflectivity that can be...
US-7,035,434 Hough transform based motion detection image recording system and method
A Hough based motion detection image recording system includes an image sensor operable to view a surveillance site and output real-time image data corresponding...
US-7,035,368 High speed parallel link receiver
A digital system aligns a set of serial data receiver demultiplex circuits, thereby aligning the bits in the data words, while maintaining separate and optimally...
US-7,035,275 Non-collaborative mechanisms for enhanced coexistence of wireless networks
When wireless communications systems are operating in the same general area, collisions between their transmissions are bound to occur. The collisions reduce the...
US-7,035,071 Current limit with adaptive cycle skipping for switching regulators
A switching regulator having a current limit with adaptive cycle skipping. A buck type switching regulator circuit is provided, including an energy storage...
US-7,035,027 Circuits to achieve high data rate writing on thin film transducer
The present invention covers circuits to achieve high data rate writing.
US-7,034,955 Using a processor enhanced memory module to accelerate hardcopy image processing within existing printer controller
The processor enhanced memory module PEMM can be incorporated into the hardcopy image processing pipeline of existing printer controllers by using the smart...
US-7,034,611 Multistage common mode feedback for improved linearity line drivers
A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is...
US-7,034,609 Switching circuits
A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry...
US-7,034,591 False-lock-free delay locked loop circuit and method
A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a...
US-7,034,583 Versatile system for output energy limiting circuitry
The present invention provides a system for limiting energy levels across the output of a driver circuitry segment (100). The system provides an output structure...
US-7,034,579 High-speed signal level detector
A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is...
US-7,034,542 Current sensing circuit and method
The present invention includes a plurality of FETs (211, 212, 213, 214, 215, 216, 217) including an operational amplifier with additional FETs (218, 219,...
US-7,034,512 Hysteretic controlled switch regulator with fixed off time
System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch...
US-7,034,415 Pivoting mirror with improved magnetic drive
A magnetic drive for providing pivotal motion to a functional surface, such as a mirror. The magnetic drive may be used to drive any torsional hinged device, but...
US-7,034,379 Carbide emitter mask etch stop
Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base...
US-7,034,364 Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection
The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more...
US-7,033,924 Versatile system for diffusion limiting void formation
Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device...
US-7,033,897 Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and...
The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced...
US-7,033,879 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a...
US-7,033,864 Grooved substrates for uniform underfilling solder ball assembled electronic devices
A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A...
US-7,032,807 Solder contact reworking using a flux plate and squeegee
Solder contacts can be formed on the conductive sites of a substrate by placing preformed solder balls on the conductive sites and then reflowing the solder...
US-7,032,430 Systems and methods for self test for a slowly varying sensor
Systems, methods and circuits for implementing a self test in a slowly varying sensor. In one particular case, a circuit is provided that includes two filters...
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