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Patent # Description
US-7,020,219 Wireless user terminal and system having high speed, high resolution, digital-to-analog converter with off-line...
A wireless communications apparatus and corresponding system having an improved DAC operable at higher speed than heretofore achievable which exploits the...
US-7,019,881 Display system with clock dropping
A display system includes a light source 110 and a spatial light modulator 122 located to receive light from the light source. The spatial light modulator (e.g.,...
US-7,019,356 Memory device with reduced cell area
The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active...
US-7,019,352 Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in semiconductor devices having...
Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion...
US-7,018,925 Post high voltage gate oxide pattern high-vacuum outgas surface treatment
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage...
US-7,018,902 Gate dielectric and method
A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or...
US-7,018,888 Method for manufacturing improved sidewall structures for use in semiconductor devices
The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor...
US-7,018,881 Suspended gate single-electron device
The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (110) located over a substrate...
US-7,018,880 Method for manufacturing a MOS transistor having reduced 1/f noise
The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming...
US-7,017,006 System and method to enable efficient communication with a dynamic information storage and retrieval system, or...
An information storage and retrieval system (40) and method for operating same has a host device (42) and an information storage device (41), which includes mass...
US-7,016,445 Apparatus for and method of clock recovery from a serial data stream
A novel and useful apparatus for and method of clock recovery from a serial data stream. The clock recovery mechanism of the present invention provides accurate...
US-7,016,402 Digital subscriber line modem with automated line connection
A DSL modem (50). The DSL modem includes a connector (62) comprising a first pair of conductors (IP.sub.1, IP.sub.2) and a second pair of conductors (OP.sub.1,...
US-7,016,245 Tracking circuit enabling quick/accurate retrieval of data stored in a memory array
An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable...
US-7,015,975 Image processing device with a processing unit that processes image data in units of one scan line
The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is...
US-7,015,850 Bandwidth limited sampling circuit of high linearity
A bandwidth limited sampling circuit of high linearity may be implemented by using a first circuit portion to limit the bandwidth of the input signals, and using...
US-7,015,727 Generating a lock signal indicating whether an output clock signal generated by a PLL is in lock with an input...
A PLL lock generator using one circuit (lock detection block) to indicate whether an output clock signal is locked to an input reference signal, and another...
US-7,015,568 System for ultraviolet atmospheric seed layer remediation
The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate...
US-7,015,534 Encapsulated MOS transistor gate structures and methods for making the same
Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by...
US-7,015,093 Capacitor integration at top-metal level with a protection layer for the copper surface
An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and...
US-7,015,088 High-K gate dielectric defect gettering using dopants
One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a...
US-7,015,068 Partial wafer processing for random size wafers
A method of processing a partial wafer in accordance with one embodiment comprises includes after of loading partial wafer into wafer table of pick and place...
US-7,013,725 System and method for regulating bridge voltage in a discontinuous-time hot-wire anemometer
In accordance with the teachings of the present invention, a system and method for regulating bridge voltage in a discrete-time hot-wire anemometer is provided....
US-7,013,416 IC with expected data memory coupled to scan data register
A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register...
US-7,013,358 System for signaling serialized interrupts using message signaled interrupts
The present invention provides a system for signaling legacy serialized interrupts within a PCI-Express environment, using message signaled interrupts. The...
US-7,012,846 Sense amplifier for a memory array
A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if...
US-7,012,717 Multi-level dither screening on a split arithmetic logic unit processor
This invention is a method of multilevel dither screening in a printer. Plural pixel values are packed into equal sections of a first data word. Corresponding...
US-7,012,467 Apparatus and method for compensating operating current in an amplifier when supply voltage varies
An apparatus for compensating operating current in an amplifier device when supply voltage to the amplifier device decreases below a predetermined value at an...
US-7,012,028 Transistor fabrication methods using reduced width sidewall spacers
Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a...
US-7,012,018 Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices
An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a...
US-7,011,415 Yokeless hidden hinge digital micromirror device
A micromirror array fabricated on a semiconductor substrate. The array is comprised of three operating layers. An addressing layer is fabricated on the...
US-7,010,722 Embedded symmetric multiprocessor system debug
A test signal multiplexer receives supplies external test signals to a selected debug master central processing unit in a symmetrical multiprocessor system and...
US-7,010,381 Versatile system for controlling semiconductor topography
The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization....
US-7,009,960 Medium access control protocol for high rate wireless personal area network
The MAC protocol of the present invention takes into account backward compatibility and conventional layering principles while introducing QoS parameters to...
US-7,009,864 Zero cancellation scheme to reduce plateline voltage in ferroelectric memory
Ferroelectric memory devices and methods are provided, wherein a cell plateline signal is applied to a ferroelectric target cell capacitor and a zero...
US-7,009,748 Resonant scanning mirror with inertially coupled activation
A system and method for providing a resonant beam sweep about a first axis. A mirror or reflective surface supported by a first pair of torsional hinges is...
US-7,009,745 Coating for optical MEMS devices
A micromechanical device having a deflectable member which contacts a stationary member. An antireflective coating is applied to portions of the micromechanical...
US-7,009,736 Tile map based multi-level supercell screening
This invention is a screening method. The input image is divided into a plurality of supercells. These supercells are divided into a plurality of individual...
US-7,009,549 Switched-capacitor circuit with scaled reference voltage
A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which...
US-7,009,450 Low distortion and high slew rate output stage for voltage feedback amplifier
A voltage feedback ("VF") operational amplifier ("op-amp") that includes a circuit operable to dynamically bias pre-driver transistors at the op amp output...
US-7,009,440 Pulse signal generator and display device
The objective of this invention is to provide a pulse signal generator with a simple constitution that can reduce the number of signals required for setting the...
US-7,009,369 Advanced monitoring algorithm for regulated power systems with single output flag
An improved method of monitoring the output power provided by a switch mode power converter that reduces the overall cost of the converter. The method includes...
US-7,007,552 Multi-channel pressure sensing apparatus
A multi-channel pressure sensor module (10) for integration in a hydraulic/electrical control unit of a vehicular braking system is shown. A body or manifold...
US-7,007,267 Transparent shared memory access in a software development system
The invention relates to a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map...
US-7,007,052 Efficient real-time computation
Systems and methods for determining coefficients a filter are disclosed. The filter coefficients are computed by determining a sine of an input value and an...
US-7,006,995 Secure distribution of digital data
A secure digital data distribution system (100) for preventing unauthorized access to digital data. The system utilizes an identification system module (116)...
US-7,006,813 Efficient charge transfer using a switched capacitor resistor
The application of a non-zero voltage offset to rotating capacitors 1111 and 1112 permit the use of a single positive voltage supply. However, the precharging of...
US-7,006,626 Subscriber interface circuit
A subscriber line interface circuit is provided that posses an output impedance that may be greater than about 2.2 Kohms at at least some frequencies associated...
US-7,006,589 Frequency synthesizer with phase restart
A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC...
US-7,006,585 Recovering data encoded in serial communication channels
A transition between values of two successive bits is detected. The bit after the transition is used as one of the recovered bits. A recovery circuit may...
US-7,006,521 External bus arbitration technique for multicore DSP device
A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems...
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