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Multiphase DC-to-DC switching power converter with leading edge and cross
A multiphase DC-to-DC synchronous power converter, which has a number of converter channels that generate a corresponding number of current sense signals,...
System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
Method and system for active noise cancellation according to a type of
Microphone signals are received from a microphone. The microphone signals represent first sound waves. A determination is made about a type of noise that likely...
High density low power scan flip-flop
A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the...
Tap with flip-flop command circuit selecting data register routing circuit
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to...
Making a plurality of integrated circuit packages
A method of making a plurality of integrated circuit packages provides a metal strip. A first leadframe having a first die pad is formed on the metal strip....
Method, system and computer program product for adjusting a convergence
plane of a stereoscopic image
First and second views of a stereoscopic image are received. In response to determining that the stereoscopic image has a predominance of foreground features, a...
Sounding reference signal user equipment specific sub-frame configuration
A method of wireless communication including a plurality of fixed basestations and a plurality of mobile user equipment with each basestation transmitting to...
Reduction of input dependent capacitor DAC switching current in flash-SAR
Circuits and methods for reducing input dependent capacitor DAC switching current in flash-successive approximation register (SAR) analog-to-digital converters...
Low clock-power integrated clock gating cell
In an integrated clock gating (ICG) cell a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to generate a latch...
System and method for balancing voltages
A circuit providing voltage cell balancing is provided. The circuit includes a cell balancing network comprising separate switching circuits, each being...
Circuit and architecture for a demodulator for a wireless power transfer
system and method therefor
A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for receiving communications from the secondary side...
Circuit and architecture for a demodulator for a wireless power transfer
system and method therefor
A primary side wireless power transmitter inductively couplable to a secondary side wireless power receiver for supplying power to the wireless power receiver...
Low resistance LDMOS with reduced gate charge
An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first...
Inner L-spacer for replacement gate flow
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner...
High sheet resistor in CMOS flow
An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with...
TSV scan cell comparator coupled to voltage reference and response
An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between...
Circuit and method for imprint reduction in FRAM memories
A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B.sub.0, B.sub.1). A...
System and method for fast modification of register content
The present invention is drawn to a register writing mechanism that does not require reading of the data in the register. In accordance with aspects of the...
LCD panel with new control line topology
A liquid crystal display (LCD) that includes a plurality of segments, and a plurality of control lines to activate the plurality of segments. Each of the...
Performing GPS operations in receiver sensor engine and position engine
Embodiments of the disclosure provide a cross coupled position engine architecture for sensor integration in a Global Navigation Satellite System. In one...
Programmable access test compression architecture input and output shift
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access...
On-chip calibration system and method for infrared sensor
A radiation sensor includes an integrated circuit radiation sensor chip (1A) including first (7) and second (8) thermopile junctions connected in series to form...
Displaying walking signals variously rotated, estimating variance,
vertical, lateral direction
A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor...
Signaling of random access preamble parameters in wireless networks
User equipment (UE)-initiated accesses within a cellular network are optimized to account for cell size and to reduce signaling overhead. A fixed set of...
Video device finishing encoding within the desired length of time
A system comprising a processor and a compression module coupled to the processor. The compression module is adapted to perform motion estimation on video data...
Electric vehicle and service equipment on a pilot wire
Electric Vehicle Service Equipment (EVSE) and Electric Vehicle (EV) are disclosed n. In an example embodiment, a modem is coupled to the pilot wire that couples...
Circuits, devices, and processes for improved positioning satellite
reception and other spread spectrum reception
An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable...
High speed, rail-to-rail CMOS differential input stage
An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output, wherein the differential input...
Relaxation oscillator with current and voltage offset cancellation
A relaxation oscillator reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current and a second current so...
Method and apparatus of fast battery charging with universal high power
Methods, electronic devices and USB charger apparatus are presented for fast USB charging, in which a high voltage master of the device detects a connected high...
An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler...
Medium voltage MOSFET device
A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are...
Metal-gate MOS transistor and method of forming the transistor with
reduced gate-to-source and gate-to-drain...
The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k...
Method for forming avalanche energy handling capable III-nitride
A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by...
Integrating multi-output devices having vertically stacked semiconductor
A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second...
Converter having partially thinned leadframe with stacked chips and
interposer, free of wires and clips
Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip...
Gang clips having distributed-function tie bars
Gang clips (500) having a flat area (510), a ridge (510a), and tie bars (530b) extending from the flat area, the end portions of the ties bars aligned in a...
Disk drive preamplifier R/C differential mode filter of power supply
A disk drive preamplifier integrated circuit. The integrated circuit comprises a differential output driver configured to drive readback data to an output load,...
Method, system and computer program product for enhancing a depth map
A first depth map is generated in response to a stereoscopic image from a camera. The first depth map includes first pixels having valid depths and second...
Processor with execution unit wait control
A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to...
X-ray sensor and signal processing assembly for an X-ray computed
An apparatus having an X-ray sensor assembly with X-ray blocking pixels divided by X-ray transmitting gaps with the X-ray blocking pixels casting an X-ray...
Fixture for test circuit board reliability testing
A fixture for securing at least one test printed circuit board assembly (PCBA) including a PCB having semiconductor devices mounted thereon during vibration or...
Access point discoverability in multi-role multi-channel devices
Systems and methods for improved access point discoverability in multi-role multi-channel devices are described. When the multi-role multi-channel device leaves...
Capacitive micromachined ultrasonic transducer (CMUT) with
through-substrate via (TSV) substrate plug
A Capacitive Micromachined Ultrasonic Transducer (CMUT) device includes at least one CMUT cell including a first substrate of a single crystal material having a...
Method, system and apparatus for carrier frequency offset correction and
A receiver is configured to use a first part of a received signal and a second part of the received signal to determine, respectively, a first estimate and a...
Coexistence method by requesting access to the channel
Systems and methods for implementing coexistence by requesting access to a channel in power line communications (PLC) are described. In an illustrative...
De-emphasis filtering audio signals in response to composite control
Digital values representing an audio signal are formed in a FM transmitter. The deviation of the amplitude of the audio signal as represented by the digital...
Timing compensation using the system clock
An integrated circuit including a plurality of internal clock generator circuits from which an internal clock is selected based on an external time reference. A...
Flip-flops with low clock power
The disclosure provides a flip-flop that utilizes low power as a result of reduced transistor count. The flip-flop includes a tri-state inverter that receives a...