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Patent # Description
US-9,430,393 System and method for managing cache
A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter...
US-9,430,346 Processor power measurement
A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The...
US-9,430,008 Apparatus and method for optimizing use of NVDC chargers
A method includes detecting removal or depletion of a power supply associated with a powered device. The powered device is configured to receive power from a...
US-9,429,971 Short-circuit protection for voltage regulators
Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error...
US-9,429,968 Power-gated electronic device
A power-gated electronic device and a method of operating the same is provided. The power-gated electronic device comprises a low drop out voltage power supply...
US-9,429,918 Atomic clocks and magnetometers with vapor cells having condensation sites in fluid communication with a cavity...
A vapor cell for installation in an atomic clock or a magnetometer. The vapor cell includes a top plate, a center plate, and a bottom plate defining a cavity...
US-9,429,645 Programmable wavelet tree
An apparatus is provided. In the apparatus, a demultiplexer is configured to receive an input signal, and each of a plurality of sample buffers are coupled to...
US-9,429,528 Determining gas absorption line from separate and alternating RF signals
A method to detect a gas absorption line that includes alternately transmitting and sweeping two radio frequency (RF) signals through an absorption cell,...
US-9,426,458 Video output supervisor
A video output supervisor includes a test region indicator for verifying that the commanded output to specific areas of a display is valid. Areas reserved...
US-9,425,955 Power line communication (PLC) network nodes using cipher then segment security
Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates...
US-9,425,871 4TX codebook enhancement in LTE
Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based...
US-9,425,811 Method and apparatus for compensating offset drift with temperature
The disclosure provides an analog to digital converter (ADC). The ADC includes a comparator that receives a threshold voltage. A set of elementary capacitors is...
US-9,425,808 Frequency detector
A frequency detection technique includes generating first and second signals such that a frequency of the first signal is the same as a frequency of the second...
US-9,425,792 Reconfigurable power switch chains for efficient dynamic power saving
Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for...
US-9,425,771 Low area flip-flop with a shared inverter
A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock...
US-9,425,739 Tunable quadrature oscillator
A tunable quadrature oscillator includes a first oscillator having an output, a second oscillator having an output, and a variable gain amplifier. The variable...
US-9,425,188 Active ESD protection circuit with blocking diode
An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a...
US-9,425,132 Stacked synchronous buck converter having chip embedded in outside recess of leadframe
A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor...
US-9,424,193 Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems
The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or...
US-9,423,808 DC to DC converter with pseudo constant switching frequency
A method for a DC to DC converter with a pseudo constant switching frequency is disclosed herein. For example, some embodiments provide a DC to DC converter...
US-9,423,459 Taps with class T0-T2 and T3, T4(W), and T5(W) capabilities
Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data...
US-9,423,458 Transporting ordered test data, mode select, ready, precharge packet bits
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to...
US-9,419,903 Structure for implementing openflow all group buckets using egress flow table entries
An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets....
US-9,419,835 System and method for preamble detection in MIMO narrowband power line communications
A PLC network system and method operative with OFDM for generating MIMO frames with suitable preamble portions configured to provide backward compatibility with...
US-9,419,788 Data transfer clock recovery for legacy systems
The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate...
US-9,419,750 NLOS wireless backhaul uplink communication
A method for uplink (UL) wireless backhaul communication at a wireless backhaul remote unit in a radio access network comprising receiving a configuration for...
US-9,419,630 Phase shifted coarse/fine clock dithering responsive to controller select signals
A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an...
US-9,419,613 Low power scheme to protect the low voltage capacitors in high voltage IO circuits
An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being...
US-9,419,594 Clock data recovery system
A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal;...
US-9,419,591 Controllable wide frequency range oscillator
A circuit includes a ring oscillator that includes a plurality of delay stages coupled in series to generate an output frequency for the ring oscillator. A...
US-9,419,509 Shared bootstrap capacitor for multiple phase buck converter circuit and methods
A multiple phase dc to dc converter with a shared bootstrap capacitor. In an embodiment, a multiple phase buck converter is disclosed including a plurality of n...
US-9,419,431 Short-circuit protection system for power converters
One example includes a power converter system. The system includes a switching circuit configured to activate at least one power supply switch in response to a...
US-9,419,075 Wafer substrate removal
A semiconductor device is formed on a semiconductor substrate, including a primary portion of the substrate. An active component of the semiconductor device is...
US-9,419,014 Alternating tap-cell strategy in a standard cell logic block for area reduction
An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a...
US-9,418,197 Method for designing diodes
A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating...
US-9,417,648 Power switch with source-bias mode for on-chip powerdomain supply drooping
This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit...
US-9,417,293 Magnetic field sensor linearization architecture and method
A method of processing an output signal and a readout circuit for a magnetic field sensor are disclosed. The purpose of the readout circuit is to generate a...
US-9,417,284 IC die with tap lock, test, scan, and up circuitry
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
US-9,417,283 Semiconductor test system and method
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response...
US-9,417,133 Infrared sensor structure and method
A radiation sensor (27) includes a radiation sensor chip (1) including first (7) and second (8) thermopile junctions connected to form a thermopile (7,8). The...
US-9,414,104 Graphics initialization for wireless display devices
A method of optimizing bandwidth of a wireless link between a display device and an image data player. The display device is configured with one or more...
US-9,413,509 Hybrid automatic repeat request acknowledge resource allocation for enhanced physical downlink control channel
A method and apparatus of wireless communication between a base station and at least one user equipment. The method includes: transmitting an enhanced physical...
US-9,413,423 SNR calculation in impulsive noise and erasure channels
A device coupled to a noisy channel having periodic impulse noise in a network may estimate an effective signal to noise ratio (SNR) by receiving a packet of...
US-9,413,383 Delta sigma modulator apparatus and method to mitigate DAC error induced offset and even order harmonic distortion
Delta sigma modulators, apparatus and methods mitigate DAC error induced offset and even order harmonic distortion in a delta sigma modulator by chopping a...
US-9,413,382 Method for calibrating a pipelined continuous-time sigma delta modulator
Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating...
US-9,413,315 Low noise amplifier with embedded filter and related wireless communication unit
In one embodiment, a WCDMA FDD system includes an embedded filter that provides a complex load to transistors in a low noise amplifier. The complex load can be...
US-9,413,300 Front-end matching amplifier
A front-end receiver includes an amplifier that has a steady gain over a wide frequency range. The disclosed amplifier adopts an architecture in which a...
US-9,413,282 Stator resistance estimation for electric motors
A method of controlling an electric motor (motor) includes providing a processor having an associated memory storing a stator resistance (Rs) estimation (RSE)...
US-9,413,239 Electronic device for average current mode DC-DC conversion
An average current mode buck-boost DC to DC converter has a buck stage coupled between an input voltage source terminal and an output terminal. A boost stage is...
US-9,413,232 Droop reduction circuit for charge pump buck converter
A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a...
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