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| Patent # | Description |
|---|---|
| US-7,023,272 |
Multi-band low noise amplifier system A low noise amplifier (LNA) operates over multiple frequency bands while occupying less silicon area than known LNA implementations. The LNA includes output... |
| US-7,023,240 |
Data-driven clock gating for a sequential data-capture device A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus... |
| US-7,023,201 |
Magnetic position sensor apparatus and method A magnetic position sensor has a stator (16', 36, 52) formed of magnetic material and a pair of magnets (14a, 14b; 34a, 34b; 54a, 54b; 64a, 64b) rotatably... |
| US-7,023,088 |
Semiconductor package, semiconductor device and electronic device An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is... |
| US-7,023,018 |
SiGe transistor with strained layers The present invention provides, in one embodiment, a P-type Metal Oxide Semiconductor (PMOS) device (100). The device (100) comprises a tensile-strained silicon... |
| US-7,023,005 |
Gain compensation for optocoupler feedback circuit A feedback circuit has an optical coupler with a feedback gain control. The feedback gain control includes an active element connected to vary current flow... |
| US-7,020,827 |
Cascade map decoder and method MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and... |
| US-7,020,822 |
Automatic repeat request for centralized channel access A method of providing an automatic repeat request (ARQ) that employs a selective repeat, enabling a transmitting medium access control (MAC) entity at a... |
| US-7,020,723 |
Method of allowing multiple, hardware embedded configurations to be
recognized by an operating system A communications system for enabling extension of an internal common bus architecture (CBA) segment of a first root physical device to an internal CBA bus... |
| US-7,020,609 |
Voice activated apparatus for accessing information on the World Wide Web This is a voice activated Hypermedia system using grammatical metadata, the system comprising: a speech user agent; a browsing module; and an information... |
| US-7,020,600 |
Apparatus and method for improvement of communication between an emulator
unit and a host device In order to reduce the traffic over the communication bus between the host processing unit and an emulator server unit during the test of a target processing... |
| US-7,020,257 |
Voice activity identiftication for speaker tracking in a packet based
conferencing system with distributed... A distributed conferencing system has a plurality of conferencing nodes to connect groups of participants to a conference. Each of the conferencing nodes... |
| US-7,020,222 |
Efficient method and system for offset phasor determination Systems and methods for determining offset phasors are disclosed. An offset vector is computed from a current channel impulse response and a previous channel... |
| US-7,020,219 |
Wireless user terminal and system having high speed, high resolution,
digital-to-analog converter with off-line... A wireless communications apparatus and corresponding system having an improved DAC operable at higher speed than heretofore achievable which exploits the... |
| US-7,019,881 |
Display system with clock dropping A display system includes a light source 110 and a spatial light modulator 122 located to receive light from the light source. The spatial light modulator (e.g.,... |
| US-7,019,356 |
Memory device with reduced cell area The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active... |
| US-7,019,352 |
Low silicon-hydrogen sin layer to inhibit hydrogen related degradation in
semiconductor devices having... Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion... |
| US-7,018,925 |
Post high voltage gate oxide pattern high-vacuum outgas surface treatment The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage... |
| US-7,018,902 |
Gate dielectric and method A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or... |
| US-7,018,888 |
Method for manufacturing improved sidewall structures for use in
semiconductor devices The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor... |
| US-7,018,881 |
Suspended gate single-electron device The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (110) located over a substrate... |
| US-7,018,880 |
Method for manufacturing a MOS transistor having reduced 1/f noise The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming... |
| US-7,017,006 |
System and method to enable efficient communication with a dynamic
information storage and retrieval system, or... An information storage and retrieval system (40) and method for operating same has a host device (42) and an information storage device (41), which includes mass... |
| US-7,016,445 |
Apparatus for and method of clock recovery from a serial data stream A novel and useful apparatus for and method of clock recovery from a serial data stream. The clock recovery mechanism of the present invention provides accurate... |
| US-7,016,402 |
Digital subscriber line modem with automated line connection A DSL modem (50). The DSL modem includes a connector (62) comprising a first pair of conductors (IP.sub.1, IP.sub.2) and a second pair of conductors (OP.sub.1,... |
| US-7,016,245 |
Tracking circuit enabling quick/accurate retrieval of data stored in a
memory array An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable... |
| US-7,015,975 |
Image processing device with a processing unit that processes image data
in units of one scan line The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is... |
| US-7,015,850 |
Bandwidth limited sampling circuit of high linearity A bandwidth limited sampling circuit of high linearity may be implemented by using a first circuit portion to limit the bandwidth of the input signals, and using... |
| US-7,015,727 |
Generating a lock signal indicating whether an output clock signal
generated by a PLL is in lock with an input... A PLL lock generator using one circuit (lock detection block) to indicate whether an output clock signal is locked to an input reference signal, and another... |
| US-7,015,568 |
System for ultraviolet atmospheric seed layer remediation The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate... |
| US-7,015,534 |
Encapsulated MOS transistor gate structures and methods for making the
same Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by... |
| US-7,015,093 |
Capacitor integration at top-metal level with a protection layer for the
copper surface An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and... |
| US-7,015,088 |
High-K gate dielectric defect gettering using dopants One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a... |
| US-7,015,068 |
Partial wafer processing for random size wafers A method of processing a partial wafer in accordance with one embodiment comprises includes after of loading partial wafer into wafer table of pick and place... |
| US-7,013,725 |
System and method for regulating bridge voltage in a discontinuous-time
hot-wire anemometer In accordance with the teachings of the present invention, a system and method for regulating bridge voltage in a discrete-time hot-wire anemometer is provided.... |
| US-7,013,416 |
IC with expected data memory coupled to scan data register A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register... |
| US-7,013,358 |
System for signaling serialized interrupts using message signaled
interrupts The present invention provides a system for signaling legacy serialized interrupts within a PCI-Express environment, using message signaled interrupts. The... |
| US-7,012,846 |
Sense amplifier for a memory array A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if... |
| US-7,012,717 |
Multi-level dither screening on a split arithmetic logic unit processor This invention is a method of multilevel dither screening in a printer. Plural pixel values are packed into equal sections of a first data word. Corresponding... |
| US-7,012,467 |
Apparatus and method for compensating operating current in an amplifier
when supply voltage varies An apparatus for compensating operating current in an amplifier device when supply voltage to the amplifier device decreases below a predetermined value at an... |
| US-7,012,028 |
Transistor fabrication methods using reduced width sidewall spacers Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a... |
| US-7,012,018 |
Metallic strain-absorbing layer for improved fatigue resistance of
solder-attached devices An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a... |
| US-7,011,415 |
Yokeless hidden hinge digital micromirror device A micromirror array fabricated on a semiconductor substrate. The array is comprised of three operating layers. An addressing layer is fabricated on the... |
| US-7,010,722 |
Embedded symmetric multiprocessor system debug A test signal multiplexer receives supplies external test signals to a selected debug master central processing unit in a symmetrical multiprocessor system and... |
| US-7,010,381 |
Versatile system for controlling semiconductor topography The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization.... |
| US-7,009,960 |
Medium access control protocol for high rate wireless personal area
network The MAC protocol of the present invention takes into account backward compatibility and conventional layering principles while introducing QoS parameters to... |
| US-7,009,864 |
Zero cancellation scheme to reduce plateline voltage in ferroelectric
memory Ferroelectric memory devices and methods are provided, wherein a cell plateline signal is applied to a ferroelectric target cell capacitor and a zero... |
| US-7,009,748 |
Resonant scanning mirror with inertially coupled activation A system and method for providing a resonant beam sweep about a first axis. A mirror or reflective surface supported by a first pair of torsional hinges is... |
| US-7,009,745 |
Coating for optical MEMS devices A micromechanical device having a deflectable member which contacts a stationary member. An antireflective coating is applied to portions of the micromechanical... |
| US-7,009,736 |
Tile map based multi-level supercell screening This invention is a screening method. The input image is divided into a plurality of supercells. These supercells are divided into a plurality of individual... |
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