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Patent # Description
US-6,988,228 Configurable scan path structure
A test structure is for a circuit (20) includes a scan configuration module (26), including routing circuitry (28) and control (30). The routing circuitry (28),...
US-6,987,799 System and method for demodulating associated information channels in direct sequence spread spectrum...
A Direct Sequence Spread Spectrum (DSSS) receiver system (100) combines and orders the soft symbols from associated information channels. The system permits a...
US-6,987,601 Damped control of a micromechanical device
Device and method for a damping function to reduce undesirable mechanical transient responses to control signals. In one aspect of the present invention, the...
US-6,987,597 Pulse width modulation sequence generation
A system and method for addressing and synchronizing a spatial light modulator (SLM) device and a scrolling color recovery (SCR) illumination system. This method...
US-6,987,382 System with functional and selector circuits connected by mode lead
A wafer of semiconductor material is processed to form integrated circuit dies. The dies are to be singulated or separated and encapsulated for sale and use as...
US-6,987,061 Dual salicide process for optimum performance
The present invention pertains to forming respective silicides on multiple transistors in a single process. High performance is facilitated with simple and...
US-6,987,039 Forming lateral bipolar junction transistor in CMOS flow
A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant...
US-6,986,142 Microphone/speaker system with context switching in processor
A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the...
US-6,986,113 Method for estimating substrate noise in mixed signal integrated circuits
A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise...
US-6,986,089 Power reduction in scannable D-flip-flop with synchronous preset or clear
In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal...
US-6,986,028 Repeat block with zero cycle overhead nesting
A digital system is provided with means and methods for executing an instruction type wherein context information that pertains to that type instruction is...
US-6,985,982 Active ports in a transfer controller with hub and ports
In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source...
US-6,985,848 Obtaining and exporting on-chip data processor trace and timing information
An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal...
US-6,985,783 Data processing device with an indexed immediate addressing mode
A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an...
US-6,985,532 Ultra wideband (UWB) transmitter architecture
System and method for analog signal generation and manipulation in an ultra-wideband (UWB) transmitter. A preferred embodiment comprises a digital portion 305 of...
US-6,985,278 Damped control of a micromechanical device
Device and method for a damping function to reduce undesirable mechanical transient responses to control signals. In one aspect of the present invention, the...
US-6,985,124 Dot matrix display device
To improve the display quality in the scanning of a dynamic drive system by effectively preventing the erroneous display of the display elements that are...
US-6,985,045 Gain control circuits for voltage controlled oscillators
A gain controlled voltage controlled oscillator. A current controlled oscillator is adapted to provide an output signal oscillating at a frequency controllable...
US-6,985,028 Programmable linear-in-dB or linear bias current source and methods to implement current reduction in a PA...
Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a...
US-6,985,006 Adjusting the strength of output buffers
The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a...
US-6,985,002 System and method for input/output induced latch up detection
The present invention is directed to a system and method of testing an integrated circuit (IC) device for potential latch-up. The system has a power supply...
US-6,985,001 Testing ICs with distributor, collector, and parallel scan paths
An integrated circuit (70) having parallel scan paths (824 842, 924 942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-6,984,857 Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating...
Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of...
US-6,984,580 Dual damascene pattern liner
An embodiment of the invention is a dual damascene layer 13 of an integrated circuit 2 containing a dual damascene pattern liner 21. Another embodiment of the...
US-6,984,152 Multifunction passive socket for flash media cards
The present invention enables the use of a single passive socket for multiple types of flash media cards. The present invention provides this by implementing...
US-6,983,450 User configurable operating system
An operating system preferably for use with a digital signal processing target is disclosed which minimizes time and space requirements on the target DSP chip....
US-6,983,441 Embedding a JTAG host controller into an FPGA design
A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development...
US-6,983,346 Reducing tag-ram accesses and accelerating cache operation during cache miss
This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache...
US-6,983,298 Method and apparatus for linear interpolation using gradient tables
This invention is a method and apparatus for interpolation which enables simpler and cost efficient implementation in hardware or software. A function table...
US-6,983,297 Shifting an operand left or right while minimizing the number of multiplexor stages
A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with...
US-6,983,032 Digital timing recovery method for communication receivers
The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network....
US-6,982,976 Datapipe routing bridge
The datapipe routing bridge is composed of three building blocks, transmitter, bridge and receiver. The bridge component provides high levels of connectivity...
US-6,982,941 Mirror detection signal generator
An amplitude variation detection circuit that can reliably detect the mirror portion independently of the type of optical recording medium, as well as a type of...
US-6,982,915 SRAM with temperature-dependent voltage control in sleep mode
An electronic device (10), comprising a plurality of data storage cells (12), collectively operable in a data access mode and separately in a sleep mode. The...
US-6,982,694 Source driver
A display device module that can supply high-speed signals with low distortion and drive high-load signal lines at high speed. A switch unit rearranges multiple...
US-6,982,662 Method and apparatus for efficient conversion of signals using look-up table
An apparatus and method for conversion of direct stream digital (DSD) signal samples to pulse code modulated (PCM) signal samples using a look-up table. The...
US-6,982,627 Low power regulated amplifier for a transponder
A transponder (1) comprising an antenna (4), a demodulator (5) and a signal processing circuit (6) which converts a modulated signal received via the antenna (4)...
US-6,982,615 System and method for threaded plunger assembly
A system and method for a plunger assembly includes a tuning slug with a bore in the stem, a tuning screw rotatably disposed in the stem, and a coupling assembly...
US-6,982,610 Termination impedance tuning circuit
An impedance adjustment system comprising current source, a first series and a second series connected string of predetermined number of resistors, a first and...
US-6,982,588 Inverse function method for semiconductor mixer linearity enhancement
The mixer circuit includes a differential rf input driver; a differential local oscillator input circuit coupled to the differential rf input driver; a...
US-6,982,448 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same
Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C.sub.FE) from hydrogen diffusion in semiconductor devices (102),...
US-6,982,400 Electrical heater apparatus
A self retaining crankcase heater (10) has a tubular casing (12) of relatively flexible, thermally conductive material in which is received a PTC element (16),...
US-6,982,377 Time-scale modification of music signals based on polyphase filterbanks and constrained time-domain processing
A time scale modification method employs separate bands obtained through an analysis polyphase filter bank with separate time-scale modification processing for...
US-6,981,204 Programmable glitch filter for an asynchronous data communication interface
An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels...
US-6,981,190 Controlling the content of specific desired memory elements when testing integrated circuits using sequential...
A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test...
US-6,981,178 Separation of debug windows by IDS bit
A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon...
US-6,981,130 Forwarding the results of operations to dependent instructions more quickly via multiplexers working in parallel
Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective ...
US-6,980,952 Source normalization training for HMM modeling of speech
A maximum likelihood (ML) linear regression (LR) solution to environment normalization is provided where the environment is modeled as a hidden (non-observable)...
US-6,980,950 Automatic utterance detector with high noise immunity
An utterance detector for speech recognition is described. The detector consists of two components. The first part makes a speech/non-speech decision for each...
US-6,980,588 Apparatus for handling high speed data communication signals and method for manufacture thereof
An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at...
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