Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: texas instruments
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,254,755 |
On-chip receiver sensitivity test mechanism An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The... |
| US-7,254,704 |
Tracing through reset A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware... |
| US-7,254,277 |
Image processing with minimization of ringing artifacts and noise A method of reducing ringing artifacts in image data that has been filtered with a high frequency emphasis filter. For each filtered data value, a local variance... |
| US-7,254,192 |
Iterative detection in MIMO systems Detection for a MIMO (multiple-input, multiple-output) wireless communications system with symbols iteratively detected in subsets with maximum likelihood hard... |
| US-7,254,131 |
Interconnected Ethernet and 1394 network A network configuration (10) including a first network medium which is a 1394 network as well as a second network medium. Each of the first and second network... |
| US-7,253,941 |
Hinge design for enhanced optical performance for a micro-mirror device An apparatus for use with a digital micro-mirror includes a hinge disposed outwardly from a substrate. The hinge is capable of at least partially supporting a... |
| US-7,253,675 |
Bootstrapping circuit capable of sampling inputs beyond supply voltage The bootstrapping circuit capable of sampling inputs beyond supply voltage includes: a bootstrapped switch MN20 coupled between an input node and an output node;... |
| US-7,253,594 |
Reducing power/area requirements to support sleep mode operation when
regulators are turned off A single sleep mode controller which ensures that there is at least a corresponding minimum voltage level across capacitors when the corresponding regulators are... |
| US-7,253,124 |
Process for defect reduction in electrochemical plating A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H.sub.2 plasma... |
| US-7,253,086 |
Recessed drain extensions in transistor device A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54.sub.x) in a... |
| US-7,253,072 |
Implant optimization scheme The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions... |
| US-7,253,054 |
One time programmable EPROM for advanced CMOS technology A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The... |
| US-7,253,049 |
Method for fabricating dual work function metal gates A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode... |
| US-7,253,043 |
Short channel semiconductor device fabrication The formation of one or more accumulation mode multi gate transistor devices is disclosed. The devices are formed so that short channel effects are mitigated. In... |
| US-7,252,773 |
Clean for high density capacitors One aspect of the invention relates to a method of cleaning high density capacitors. According to the method, the capacitors are cleaned with a plasma that... |
| US-7,252,395 |
MEMS device deflection stop A micromirror array fabricated on a semiconductor substrate. The array is comprised of three operating layers. An addressing layer is fabricated on the... |
| US-7,252,391 |
Method of producing an image A method of producing an image comprising impinging a beam of light on first region of a dynamic filter. The dynamic filter comprising at least two regions... |
| US-7,251,091 |
Current-sense bias circuit for a magnetoresistive head and method of
sensing a current therethrough The present invention provides a current-sense bias circuit for use with a magnetoresistive head. In one embodiment, the current-sense bias circuit includes a... |
| US-7,250,705 |
Resonant oscillating device actuator structure A torsional hinged resonant device having an improved anchor support for providing inertia drive. The area by the anchors connecting the torsional hinges to the... |
| US-7,250,372 |
Method for BARC over-etch time adjust with real-time process feedback A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The... |
| US-7,250,349 |
Method for forming ferroelectric memory capacitor A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer,... |
| US-7,250,334 |
Metal insulator metal (MIM) capacitor fabrication with sidewall spacers
and aluminum cap (ALCAP) top electrode A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the... |
| US-7,248,849 |
Frequency domain training of prefilters for receivers A prefilter is trained as follows. The frequency response B of a conditioned channel is determined without reference to the prefilter, and the frequency response... |
| US-7,248,651 |
Low complexity high performance decoder and method of decoding for
communications systems using... A reduced search space minimum distance decoding algorithm provides average probability of error performance close to that of optimal MAP decoding. The decoding... |
| US-7,248,105 |
Method and circuit for input offset correction in an amplifier circuit A method and circuit for eliminating input voltage offset in an amplifier circuit are provided. An exemplary offset correction circuit is configured with DC... |
| US-7,247,535 |
Source/drain extensions having highly activated and extremely abrupt
junctions A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe... |
| US-7,246,330 |
Apparatus and method for detecting body diode conduction in a
semiconductor device An apparatus is for detecting body diode conduction in a semiconductor device that includes first regions fixed with a substrate having an upper surface to... |
| US-7,246,025 |
Method and apparatus for synchronizing signals in a testing system The preferred embodiments of the present invention provide approaches for synchronizing signals in a testing system. In some embodiments, the timing signal... |
| US-7,245,946 |
Optimal power saving scheduler for 802.11e APSD A new system and method is described, utilizing a scheduler based on a transmission power consumption calculation and prioritizing algorithm. The system utilizes... |
| US-7,245,674 |
Method and system for providing low power WLAN receiver A method and system for conserving power in a WLAN receiver is provided by a channel estimator for detecting transmitted errors in a transmitted packet and... |
| US-7,245,466 |
Pumped SCR for ESD protection An ESD protection device can include a silicon-controlled rectifier (SCR) and an external pumping circuit. The external pumping circuit can be used to forward... |
| US-7,245,173 |
Method to reduce integrated circuit power consumption by using
differential signaling within the device A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling... |
| US-7,245,129 |
Apparatus for and method of cable diagnostics utilizing time domain
reflectometry A novel mechanism for performing high accuracy cable diagnostics. The mechanism utilizes time domain reflectometry (TDR) to detect and identify cable faults,... |
| US-7,245,006 |
Palladium-spot leadframes for high adhesion semiconductor devices and
method of fabrication A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an... |
| US-7,244,995 |
Scrambling method to reduce wordline coupling noise A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702,... |
| US-7,244,664 |
Method for dicing and singulating substrates The present invention provides, in one embodiment, a semiconductor wafer (100) dicing process. The dicing process comprises removing circuit features (120) from... |
| US-7,244,654 |
Drive current improvement from recessed SiGe incorporation close to gate A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to... |
| US-7,244,651 |
Fabrication of an OTP-EPROM having reduced leakage current The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be... |
| US-7,244,642 |
Method to obtain fully silicided gate electrodes The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a... |
| US-7,244,636 |
Semiconductor assembly for improved device warpage and solder ball
coplanarity A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is... |
| US-7,243,281 |
Serial burn-in monitor There is provided a burn-in monitor for testing modules on an Integrated Circuit (IC), and a corresponding method. The burn-in monitor comprises: a Serial Test... |
| US-7,243,058 |
Method and circuit for operating a voice coil actuator of a mass data
storage device A circuit (90) and method are presented to accurately determine a BEMF voltage of a VCM coil (20) after termination of a driving current in a first current... |
| US-7,242,565 |
Thermal shut-down circuit A primary current circuit 42 that outputs a primary current IPTAT proportional to the primary coefficient of temperature, secondary current circuit 43 outputs a... |
| US-7,242,544 |
Apparatus and method for applying write signals for driving a write head An apparatus for applying write signals including a first write signal and a second write signal to write information to a memory device includes a current... |
| US-7,242,515 |
Structure and method for reducing thermal stresses on a torsional hinged
device Method and structure for mounting a torsional hinged device, such as a mirror, having a first TCE (thermal coefficient of expansion) on a substrate having a... |
| US-7,242,330 |
Dynamic compensation of analog-to-digital converter (ADC) offset errors
using filtered PWM A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing... |
| US-7,242,227 |
Common mode stabilization circuit for differential bus networks A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal... |
| US-7,242,211 |
Hierarchical link instruction register core/embedded core wrapper enable
signals A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing... |
| US-7,241,690 |
Method for conditioning a microelectronics device deposition chamber The present invention provides, in one aspect, a method of conditioning a deposition chamber 100. An undercoat is placed on the walls of a deposition chamber 100... |
| US-7,241,663 |
Maskless multiple sheet polysilicon resistor The present invention facilitates semiconductor fabrication of semiconductor devices having polysilicon resistors. An oxide layer is formed over a semiconductor... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.