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Patent # Description
US-7,034,611 Multistage common mode feedback for improved linearity line drivers
A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is...
US-7,034,609 Switching circuits
A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry...
US-7,034,591 False-lock-free delay locked loop circuit and method
A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a...
US-7,034,583 Versatile system for output energy limiting circuitry
The present invention provides a system for limiting energy levels across the output of a driver circuitry segment (100). The system provides an output structure...
US-7,034,579 High-speed signal level detector
A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is...
US-7,034,542 Current sensing circuit and method
The present invention includes a plurality of FETs (211, 212, 213, 214, 215, 216, 217) including an operational amplifier with additional FETs (218, 219,...
US-7,034,512 Hysteretic controlled switch regulator with fixed off time
System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch...
US-7,034,415 Pivoting mirror with improved magnetic drive
A magnetic drive for providing pivotal motion to a functional surface, such as a mirror. The magnetic drive may be used to drive any torsional hinged device, but...
US-7,034,379 Carbide emitter mask etch stop
Bipolar transistors and methods for fabricating bipolar transistors are disclosed wherein an emitter-base dielectric stack is formed between emitter and base...
US-7,034,364 Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection
The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more...
US-7,033,924 Versatile system for diffusion limiting void formation
Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device...
US-7,033,897 Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and...
The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced...
US-7,033,879 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a...
US-7,033,864 Grooved substrates for uniform underfilling solder ball assembled electronic devices
A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A...
US-7,032,807 Solder contact reworking using a flux plate and squeegee
Solder contacts can be formed on the conductive sites of a substrate by placing preformed solder balls on the conductive sites and then reflowing the solder...
US-7,032,430 Systems and methods for self test for a slowly varying sensor
Systems, methods and circuits for implementing a self test in a slowly varying sensor. In one particular case, a circuit is provided that includes two filters...
US-7,032,204 Layout of network using parallel and series elements
Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically...
US-7,032,159 Error correction code parameter selection in a communication system
A method is disclosed for providing data for automatically estimating channel performance if different parameters of a Reed-Solomon (RS) code are used in a...
US-7,031,916 Method for converging a G.729 Annex B compliant voice activity detection circuit
A method of initializing an ITU Recommendation G.729 Annex B voice activity detection (VAD) device is disclosed, having the steps of (1) extracting a set of...
US-7,031,863 Variable condition responsive sense system and method
Signal conditioning of multiple sense elements is shown for providing information to a system requiring high accuracy and robust fault coverage. A first signal...
US-7,031,457 Programmable peak detector for use with zero-overhead Class G line drivers
A digital input signal is analyzed by a peak detector (210) configurable to trigger a first logic signal (260) if the peak detector detects the digital input...
US-7,031,400 Method of selecting a PCM modem signal constellation in relation to channel impairments
Disclosed are methods of selecting a multi-dimensional signal constellation in relation to impairments in a communication system having a data frame consisting...
US-7,031,380 Multi-client ADSL modem
A multi-client ADSL modem network (10) that can be configured for a home or office network when multiple ADSL client modems (18) are installed in different...
US-7,031,379 Time domain equalizer for DMT modulation
A method for deriving coefficients for a time domain equalizer function (24) as implemented by a digital signal processor (35) in a DSL modem (20) is disclosed....
US-7,031,374 System and method for selecting sample streams in direct sequence spread spectrum communications
A RAKE receiver with demodulating fingers is presented having the capability to assign a specific sample stream, from among a plurality of received sample...
US-7,031,163 Mechanical cooling fin for interconnects
In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom...
US-7,030,792 Suppressing digital-to-analog converter (DAC) error
A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that...
US-7,030,659 Signal switch with reduced on resistance and undershoot protection
An electronic switch applies ground potential to the backgate of a MOS pass transistor when the transistor is in the off state and the switch is open, during...
US-7,030,038 Low temperature method for forming a thin, uniform oxide
This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low...
US-7,029,972 Method of manufacturing a metal-insulator-metal capacitor
The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory...
US-7,029,967 Silicide method for CMOS integrated circuits
A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions...
US-7,029,932 Circuit and method for measuring contact resistance
Parametric testing of an integrated circuit chip includes pressing first, second, and third contact elements (PRB-1,2,3) against first, second and third...
US-7,029,925 FeRAM capacitor stack etch
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM...
US-7,028,396 Semiconductor chip pick and place process and equipment
A process and tooling for removing a semiconductor chip (31) from a handling tape (321) without damage to either the chip or tape by one or more horizontal beam...
US-7,028,294 Linking of applications into devices having overlays and shadow memories
In one embodiment a method for handling shadow or overlay memories is described wherein a linker contains a description of the memory of a target embedded system...
US-7,028,272 Reducing cell library development cycle time
An integrated tool which allows layouts for cells to be generated using a combination of synthesis, migration and manual approaches. In an embodiment, a...
US-7,028,198 Processor having real-time power conservation
A processor, comprising a monitor for, depending on the respective embodiment, measuring the relative amount of idle time, activity time, or idle time and...
US-7,028,130 Generating multiple traffic classes on a PCI Express fabric from PCI devices
A system having a PCI Express fabric and PCI devices connected thereto transmits data from the PCI devices having PCI Express traffic classes assigned. A PCI...
US-7,028,118 Multi-channel buffered serial port debugging
In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many...
US-7,027,946 Broadside compare with retest on fail
A tester routine is provided that evaluates multiple test pins, on multiple devices under test, at the same time and only if a fail occurs does any evaluation...
US-7,027,659 Method and apparatus for generating video images
A method and system for generating a video image is disclosed in which an object is monitored with a video camera to produce a sequence of video frames. Each of...
US-7,027,589 Single-ended loop test circuitry in a central office DSL modem
A central office modem (50) that includes the capability of single-ended loop testing (SELT) is disclosed. The modem (50) includes a digital signal processor...
US-7,027,522 Systems for data transmission
A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting symbols on a set of at least three...
US-7,027,492 Wireless communication system with processor requested RAKE finger tasks
A wireless base station (20). The base station comprises at least one receive antenna (AT.sub.RXn) for receiving communication signals from at least one...
US-7,027,447 Communications interface between clock domains with minimal latency
A network switch system (10) is disclosed, in which a plurality of switch fabric devices (20) are interconnected according to a ring arrangement, each of the...
US-7,027,346 Bit line control for low power in standby
The present invention achieves technical advantages as embodiments of an SRAM cell (20, 30) having the bit line voltage (BLB/BLB) controlled during standby, such...
US-7,027,275 Electrostatic discharge protection circuit with feedback enhanced triggering
A feedback enhanced triggering device for an electrostatic discharge protection circuit includes: a first inverter 30b having an output coupled to an input of a...
US-7,026,854 System for producing high-voltage, low-power driver circuitry
The present invention provides a system for producing high voltage, low power driver circuitry (300) that addresses a number of disparate design requirements....
US-7,026,838 Versatile system for accelerated stress characterization of semiconductor device structures
The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the...
US-7,026,833 Multiple-chip probe and universal tester contact assemblage
A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on one surface a plurality of protruding...
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