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Patent # Description
US-7,009,549 Switched-capacitor circuit with scaled reference voltage
A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which...
US-7,009,450 Low distortion and high slew rate output stage for voltage feedback amplifier
A voltage feedback ("VF") operational amplifier ("op-amp") that includes a circuit operable to dynamically bias pre-driver transistors at the op amp output...
US-7,009,440 Pulse signal generator and display device
The objective of this invention is to provide a pulse signal generator with a simple constitution that can reduce the number of signals required for setting the...
US-7,009,369 Advanced monitoring algorithm for regulated power systems with single output flag
An improved method of monitoring the output power provided by a switch mode power converter that reduces the overall cost of the converter. The method includes...
US-7,007,552 Multi-channel pressure sensing apparatus
A multi-channel pressure sensor module (10) for integration in a hydraulic/electrical control unit of a vehicular braking system is shown. A body or manifold...
US-7,007,267 Transparent shared memory access in a software development system
The invention relates to a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map...
US-7,007,052 Efficient real-time computation
Systems and methods for determining coefficients a filter are disclosed. The filter coefficients are computed by determining a sine of an input value and an...
US-7,006,995 Secure distribution of digital data
A secure digital data distribution system (100) for preventing unauthorized access to digital data. The system utilizes an identification system module (116)...
US-7,006,813 Efficient charge transfer using a switched capacitor resistor
The application of a non-zero voltage offset to rotating capacitors 1111 and 1112 permit the use of a single positive voltage supply. However, the precharging of...
US-7,006,626 Subscriber interface circuit
A subscriber line interface circuit is provided that posses an output impedance that may be greater than about 2.2 Kohms at at least some frequencies associated...
US-7,006,589 Frequency synthesizer with phase restart
A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC...
US-7,006,585 Recovering data encoded in serial communication channels
A transition between values of two successive bits is detected. The bit after the transition is used as one of the recovered bits. A recovery circuit may...
US-7,006,521 External bus arbitration technique for multicore DSP device
A digital signal processing system includes multiple processor subsystems, an external input/output port (XPORT), and an XPORT arbiter. The processor subsystems...
US-7,006,423 Mark detecting circuit for an optical disk
A mark detecting circuit that stably and reliably detects the marks for address information from an optical disk having tracks formed in a spiral shape and...
US-7,006,313 Circuit and method to match common mode flex impedance and to achieve symmetrical switching voltage outputs of...
A write driver 100, 200, 300 is implemented to provide near-ground common mode output voltages to produce a more symmetrical head voltage swing (i.e. .+-.0.4V...
US-7,006,268 Bracket for supporting a torsional hinge mirror with reduced hinge stress
The present invention provides methods and apparatus for combining a pivoting mirror and support bracket such that the support bracket transmits little or no...
US-7,006,115 Supporting variable line length in digital display timing controllers using data enable signal
A digital display unit which receives horizontal lines of unequal length in a V-active region and computes an average length of the lines. The average is used to...
US-7,006,023 Sigma-delta modulator with passive bandpass loop filter
Digitizing a signal includes sampling and holding an analog signal to yield a sampled signal, where the analog signal includes information. The sampled signal is...
US-7,005,752 Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers...
US-7,005,745 Method and structure to reduce risk of gold embrittlement in solder joints
A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention...
US-7,005,742 Socket grid array
Assembly methods and semiconductor device assemblies are disclosed in which corresponding IC sockets and PCB projections are used for alignment and bond...
US-7,005,719 Integrated circuit structure having a flip-chip mounted photoreceiver
An apparatus comprising an integrated circuit structure is provided. The integrated circuit structure comprises a substrate and a photoreceiver. The substrate...
US-7,005,365 Structure and method to fabricate self-aligned transistors with dual work function metal gate electrodes
The present invention provides, in one embodiment, a method (100) of forming dual work function metal gate electrodes in a semiconductor device. The method...
US-7,005,361 Providing high precision resistance in an integrated circuit using a thin film resistor of controlled dimension
In one embodiment, an integrated circuit includes a thin film resistor, which includes a resistor material that has been deposited on a substrate surface within...
US-7,005,354 Depletion drain-extended MOS transistors and methods for making the same
Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with...
US-7,005,101 Virtual gate design for thin packages
The mold for a thin package uses a gate which has a high aspect ratio, about 30 degrees or greater throughout the length of the gate. Additionally, the depth of...
US-7,003,707 IC tap/scan test port access with tap lock circuitry
Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core...
US-7,003,276 Subsampling communication receiver architecture with gain control and RSSI generation
A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, ....
US-7,003,016 Maximum likelihood timing synchronizers for sampled PSK burst TDMA system
A method of producing a correction signal includes receiving a predetermined data sequence (500). The data sequence is sampled at predetermined times, thereby...
US-7,002,975 Multiprocessor network node failure detection and recovery
In a node failure detection technique at least one supervisory data processing node periodically transmits a receipt acknowledge data packet to each other data...
US-7,002,930 Method of optimal power distribution for communication systems
A method of optimally distributing signal power for multiple users over a xDSL or wireless channel considers uses computationally efficient tools to achieve...
US-7,002,506 Providing pipe line ADC with acceptable bit error and power efficiency combination
A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge...
US-7,002,496 All-digital calibration of string DAC linearity using area efficient PWL approximation: eliminating hardware...
A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of...
US-7,002,406 Loop filter for class D amplifiers
A class-D amplifier circuit (30; 30') providing improved open-loop error for base-band frequencies, such as the audio band, is disclosed. The amplifier circuit...
US-7,002,369 Implementing complex clock designs in field programmable devices
An aspect of the present invention simplifies the implementation of complex clock designs in field programmable devices (FPD). To implement a circuit logic...
US-7,002,240 Semiconductor leadframe for staggered board attach
The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities,...
US-7,002,129 Charge detection node with reset feed-through shielding gate
The charge detection device includes a floating diffusion, a reset transistor, a feed through shielding transistor, and a bias tracking voltage reference...
US-7,001,848 Hydrogen plasma photoresist strip and polymeric residue cleanup process for oxygen-sensitive materials
Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor...
US-7,001,821 Method of forming and using a hardmask for forming ferroelectric capacitors in a semiconductor device
Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or...
US-7,000,822 Wire bond integrity test system
An improved bond integrity test system is provided by eliminating the spring loaded wire spool cover which contributes to particulate matter, and by addition of...
US-7,000,478 Combined pressure and temperature transducer
A combined pressure and temperature transducer (10) particularly adapted for high temperature fluids has a sensing element assembly mounted at the tip of a...
US-6,999,981 Circuit for computing the absolute value of complex numbers
An apparatus (100) for computing the absolute value of a complex number includes separate squaring units (110, 115) for the real and imaginary parts. A square...
US-6,999,799 System and method for adaptive deep-sleep slotted operation
A system and method have been provided that permit a mobile station to enter a deep-sleep slotted mode of operation in response to detected patterns of low...
US-6,999,534 Method for mitigating DC offset in a sign bit correlator
A method 10 is provided to mitigate DC offset in a sign bit correlator associated with a packet detection circuit. The input sign pattern is monitored; and if a...
US-6,999,530 Using SISO decoder feedback to produce symbol probabilities for use in wireless communications that utilize...
In a wireless communication receiver (31) of a wireless communication system that utilizes transmit diversity and turbo coding, symbol probabilities (45, 46) are...
US-6,999,508 Multi-channel frequency domain equalizer for radio frequency interference cancellation
A multichannel frequency domain equalizer improves the subchannel signal to noise ratio by canceling correlated noise that is caused by deterministic spreading...
US-6,999,215 Multilayered oscillating functional surface
A multilayered torsional hinged scanning mirror including a hinge layer with a mirror attaching member pivotally supported by torsional hinges. A mirror layer is...
US-6,998,910 Amplifier using delta-sigma modulation
An amplifier and a driver circuit therefor are presented for driving a load according to a system analog input. The amplifier comprises a passive delta-sigma...
US-6,998,904 Circuit and method for turn-on of an internal voltage rail
The circuit and method for turning on an internal voltage rail includes: coupling a first transistor between a power supply node and an internal voltage rail...
US-6,998,898 Programmable front end for a receiving channel
The present invention discloses a circuit used to couple an input signal to an amplifier circuit. The circuit may contain a diode bridge coupled to an adjustable...
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