Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: texas instruments
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,176,985 |
Clamping circuit for video signals An apparatus, system and method for clamping a video signal input to a coupling capacitor (215) for providing a clamping voltage. A charging current is applied... |
| US-7,176,821 |
Reduced area digital sigma-delta modulator A digital sigma-delta modulator requiring minimal die area and dissipating minimal power is formed with a plurality of integration stages coupled in tandem... |
| US-7,176,815 |
Video coding with CABAC Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus... |
| US-7,176,760 |
CMOS class AB folded cascode operational amplifier for high-speed
applications An operational amplifier (1A or 1B) includes a translinear transconductance stage (2B or 2C) receiving an input signal (Vin) of the operational amplifier and... |
| US-7,176,749 |
Avoiding excessive cross-terminal voltages of low voltage transistors due
to undesirable supply-sequencing in... Ensuring sufficient bias current is provided to a portion of a circuit containing low voltage transistors operating with a high supply voltage. Such a sufficient... |
| US-7,176,742 |
Bootstrapped switch with an input dynamic range greater than supply
voltage A bootstrapping circuit capable of sampling inputs beyond a supply voltage which includes a bootstrapped switch coupled between an input node and an output node,... |
| US-7,176,726 |
Integrated loss of signal detection with wide threshold range and precise
hysteresis A loss-of-signal (LOS) detector includes a variable gain amplifier with an input receiving an input signal, a threshold comparator with a first input receiving a... |
| US-7,176,091 |
Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer... |
| US-7,176,076 |
Semiconductor CMOS devices and methods with NMOS high-k dielectric present
in core region that mitigate damage... The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS... |
| US-7,174,468 |
Methodology for coordinating and tuning application power Methods and systems are provided for developing a power management strategy for an application as the application is developed. These methods and systems broadly... |
| US-7,174,194 |
Temperature field controlled scheduling for processing systems A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management... |
| US-7,173,919 |
Random access preamble coding for initiation of wireless mobile
communications sessions A method of operating a wireless communications unit (UE) to request a connection with a base station (10) is disclosed. The wireless unit (UE) receives a signal... |
| US-7,173,727 |
Path to trapezoid decomposition of polygons for printing files in a page
description language A computer implemented method of rasterizing a page in a page description language efficiently utilizes the resources of a multiprocessor integrated circuit by... |
| US-7,173,719 |
Integrated raster image processor and electro-photographic engine
controller This invention comprises a converged printer architecture for controlling both electro-photographic (EP) processing and raster image processing (RIP) of data for... |
| US-7,173,668 |
Equilibrium based horizontal sync detector for video decoder The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the... |
| US-7,173,601 |
Method and apparatus for providing position feedback of an optical
dithering element According to one embodiment, a method for providing position feedback for a device includes providing a photointerrupter having a light-emitting diode, a... |
| US-7,173,498 |
Reducing the coupling between LC-oscillator-based phase-locked loops in
flip-chip ASICs Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit... |
| US-7,173,340 |
Daisy chaining of serial I/O interface on stacking devices A bottom die and a top die stacked on the bottom die are configured to provide a daisy chain function. Both die include an input/output function control bonding... |
| US-7,173,296 |
Reduced hydrogen sidewall spacer oxide An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD... |
| US-7,172,936 |
Method to selectively strain NMOS devices using a cap poly layer The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of... |
| US-7,171,577 |
Methods and apparatus for a system clock divider A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively... |
| US-7,171,497 |
Progressive extended compression mask for dynamic trace This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least... |
| US-7,171,435 |
Circuits, systems, and methods implementing approximations for logarithm,
inverse logarithm, and reciprocal A digital signal system (30) for determining an approximate logarithm of a value of x having a base b is described. The system comprises circuitry for storing x... |
| US-7,171,335 |
System and method for the analysis of semiconductor test data According to one embodiment, a method of analyzing semiconductor test data includes receiving a plurality of raw data entries from a testing system. Each raw... |
| US-7,171,068 |
Method to improve an extinction ratio of an optical device A method to improve an extinction ratio of an optical device, the method includes positioning at least a majority of a plurality of micro-mirrors in an off-state... |
| US-7,171,035 |
Alignment mark for e-beam inspection of a semiconductor wafer An alignment mark to be used in conjunction with e-beam imaging to identify specific feature locations on a chip including a unique "L" shaped pattern of... |
| US-7,170,962 |
Data transmission A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each... |
| US-7,170,937 |
Complexity-scalable intra-frame prediction technique This invention is a method of encoding intra frames when encoding a motion picture. A set of intra frame prediction modes includes a low-complexity subset. A... |
| US-7,170,927 |
Methods and apparatus for an ADSL transceiver An ADSL transceiver hybrid circuit uses one or more isolated couplers (optical couplers, capacitors, or the like) configured to minimize the transmit signal... |
| US-7,170,861 |
Distributed device identifier numbering and total device counting
algorithm with smart time division... A distributed method and apparatus for assigning a unique identifier number to devices connected in a sequential fashion and determining a total device count is... |
| US-7,170,828 |
Removable face plate compressed digital music player This invention comprises a two part audio system in which all of the processing power is allocated to a small, lightweight satellite part that is the face unit.... |
| US-7,170,769 |
High performance and reduced area architecture for a fully parallel search
of a TCAM cell A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one... |
| US-7,170,667 |
Lifetime improvement in microstructures with deformable elements A microelectromechanical device with a plastically deformable element of is exposed to illumination light so as to elongate the lifetime of the device on the... |
| US-7,170,628 |
Efficient processing of images in printers A printer controller in which the image data received in indexed format is stored only in indexed format. The image data is converted to long format when... |
| US-7,170,277 |
Shield for tester load boards The invention provides tester load board shields (10, 40) for attachment to tester load boards. The shields (10, 40) of the invention protect from physical... |
| US-7,169,659 |
Method to selectively recess ETCH regions on a wafer surface using capoly
as a mask The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while... |
| US-7,169,345 |
Method for integrated circuit packaging According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool... |
| US-7,167,532 |
Method and apparatus for generating an oversampling clock signal A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL.... |
| US-7,167,522 |
Video deblocking filter Decomposition of deblocking filters used in block-based video compression allows reduction of computational redundancies. |
| US-7,167,350 |
Design implementation to suppress latchup in voltage tolerant circuits The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard... |
| US-7,167,334 |
Digital actuator control and method Disclosed are methods and apparatus for digital control of a head-disk assembly actuator with dynamic velocity compensation. In preferred methods of the... |
| US-7,167,148 |
Data processing methods and apparatus in digital display systems Data processing methods and apparatus used in digital display system transpose pixel-by-pixel data into bitplane-by-bitplane data. The methods and apparatus are... |
| US-7,167,143 |
Method and system for determining characteristics of optical signals on
spatial light modulator surfaces The present application describes a system and method for determining characteristics (e.g., exact band location, orientation and height and the spot shape and... |
| US-7,167,056 |
High performance analog charge pumped phase locked loop (PLL) architecture
with process and temperature... The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature... |
| US-7,167,038 |
Power efficiency control output buffer A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the... |
| US-7,167,017 |
Isolation cell used as an interface from a circuit portion operable in a
power-down mode to a circuit portion... An isolation cell provided between a first module (which can operate in either a power-up mode or a power down mode) and a second module. According to an aspect... |
| US-7,166,903 |
Drain extended MOS transistors with multiple capacitors and methods of
fabrication Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate... |
| US-7,166,858 |
Variable capacitor single-electron device The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a... |
| US-7,166,546 |
Planarization for integrated circuits A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In... |
| US-7,166,481 |
Method for evaluating and modifying solder attach design for integrated
circuit packaging assembly A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.