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Patent # | Description |
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US-7,071,013 |
Fixture and method for uniform electroless metal deposition on integrated
circuit bond pads A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides... |
US-7,070,088 |
Method of semiconductor device assembly including fatigue-resistant
ternary solder alloy Method for assembling a semiconductor device having fatigue-resistant interconnection fillet provides a semiconductor chip with at least one solder bump... |
US-7,069,493 |
Semiconductor memory device equipped with error correction circuit The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that... |
US-7,069,485 |
Reading data from a memory with a memory access controller A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is... |
US-7,069,415 |
System and method to automatically stack and unstack Java local variables A processor preferably comprises a processing core that generates memory addresses to access a memory and on which a plurality of methods operate, a cache... |
US-7,069,102 |
System and method to customize bond programs compensating integrated
circuit bonder variability A computerized system and method for customizing bond programs in order to compensate first for variabilities in an integrated circuit (IC) "slave" bonder, and... |
US-7,068,678 |
Method and apparatus for coordinating multi-point to point communications
in a multi-tone data transmission system A variety of bi-directional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a... |
US-7,068,617 |
Low complexity CDMA receiver A CDMA receiver is provided which is operable to receive a CDMA encoded signal and decode the information therein utilizing a selected code. The systems utilizes... |
US-7,068,458 |
Preamplifier fly height control (FHC) driver and sensing circuit Managing temperature of a read/write head (120) in a disk drive system in which there is a power variance due to different operation modes. A circuit device... |
US-7,068,454 |
Hard disk storage system including a first transistor type and a second
transistor type where a first voltage... A write driver produces balanced voltages across head by using the input write data drive transistors of a slower transistor type (typically PNP) on one half of... |
US-7,068,450 |
High speed pre-driver with voltage reference for thin film head write
driver A preamplifier device (26) for a thin film transducer disk drive system having operation speeds up to and greater than 2 Gb/s. The device (26) includes a low... |
US-7,068,270 |
Design of integrated circuit package using parametric solids modeller A computer is used to model objects by accepting commands from a user. The object is altered in response to the commands. Dimensions are formed between the... |
US-7,068,203 |
Switched-capacitor circuits with reduced finite-gain effect Operational amplifier circuits (20, 30) including error capacitors (C.sub.3, C13) for storing finite gain effect error voltages for correction of output voltages... |
US-7,068,108 |
Amplifier apparatus and method An amplifier apparatus having a gain programmable in discrete increments includes: (a) an operational amplifier having a first and second input and an output;... |
US-7,068,103 |
Operational transconductance amplifier input driver for class D audio
amplifiers An audio preamplifier (10) based on an operational transconductance amplifier, in combination with a class D audio output amplifier (12) is disclosed. The input... |
US-7,068,056 |
System and method for the probing of a wafer In one embodiment, a method for probing a wafer includes providing a plurality of pressure sensors on a surface of a probe card holding tray, positioning a probe... |
US-7,067,441 |
Damage-free resist removal process for ultra-low-k processing A process for removing resist (114) from a CDO dielectric material (110) that uses a non-damaging plasma in a reducing atmosphere under high power and using a... |
US-7,067,435 |
Method for etch-stop layer etching during damascene dielectric etching
with low polymerization The present invention provides a method for etching a substrate 100. The method includes conducting a first etch through a dielectric layer 130 located over an... |
US-7,067,434 |
Hydrogen free integration of high-k gate dielectrics The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this... |
US-7,067,015 |
Modified clean chemistry and megasonic nozzle for removing backside CMP
slurries A cleaning chemistry for lowering defect levels on the backside of a semiconductor wafer after chemical mechanical planarization (CMP). In a preferred embodiment... |
US-7,066,608 |
Lamp reflector assembly A lamp assembly having a reflector (102) holding a lamp element, or burner (104). The reflector (102) typically is an ellipse, with the burner arc positioned at... |
US-7,066,605 |
Color recapture for display systems A sequential color display system using a white light source to create a full color image projected onto an image plane. A dynamic filter, typically a series of... |
US-7,065,699 |
Using quadrant shifting to facilitate binary arithmetic with two's
complement operands Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an... |
US-7,065,692 |
IC with external register present lead connected to instruction register An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test... |
US-7,065,669 |
System and method for providing a write strobe signal to a receiving
element before both an address and data signal A method and apparatus is provided for that includes an improved special function register (SFR) access scheme by using a clock tree distribution process. In... |
US-7,065,498 |
Supply of digital audio and video products A server for a merchant computer system, the server comprising: a file store for storing a range of audio/video products in respective product files; a dialogue... |
US-7,065,380 |
Software partition of MIDI synthesizer for HOST/DSP (OMAP) architecture A system and method implements optimal task partitioning between a general purpose processor (GPP) and a digital signal processor (DSP) to replace a fixed... |
US-7,065,172 |
Precision jitter-free frequency synthesis An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1, CLK2) at a... |
US-7,065,166 |
Wireless receiver and method for determining a representation of noise
level of a signal A wireless receiver for receiving an incoming signal having spatial and temporal diversity. The receiver uses noise-based prescaling of multiple receiver chain... |
US-7,065,147 |
System and method of data communication using turbo trellis coded
modulation combined with constellation... A technique that combines a turbo trellis coded modulation (TTCM) coding scheme with constellation shaping and precoding schemes to implement a binary coded... |
US-7,064,694 |
Multi-cycle, multi-slope analog to digital converter A multi-cycle, multi-slope analog to digital converter overlaps charge and discharge periods to reduce latency to the end of the measurement following a sampling... |
US-7,064,682 |
Relaxation oscillator based keypad decoder The keypad interface element of this invention uses a relaxation oscillator and a digital keypad processor having a counter/timer to decode specific keys. The RC... |
US-7,064,607 |
Bias system and method A bias device that modifies the bias of a device based on an input signal to the device. The device may have a fixed bias, and the bias device can be connected... |
US-7,064,593 |
Bus-hold circuit A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current `I.sub.off` specification without incorporating a diode in pull-up... |
US-7,064,587 |
Output Buffer A low-noise output buffer for a digital signal is based on an analog amplifier having bandwidth greater than the switching rate of the digital logic signal. A... |
US-7,064,399 |
Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer... |
US-7,064,043 |
Wafer bonded MOS decoupling capacitor A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the... |
US-7,064,039 |
Method to produce localized halo for MOS transistor Methods are discussed for forming a localized halo structure and a retrograde profile in a substrate of a semiconductor device. The method comprises providing a... |
US-7,064,008 |
Semiconductor leadframes plated with thick nickel, minimum palladium, and
pure tin A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal; a plated layer of pure... |
US-7,062,762 |
Partitioning symmetric nodes efficiently in a split register file
architecture The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of... |
US-7,062,680 |
Expert system for protocols analysis An expert system that provides an analysis of protocol exchanges and protocol relationships across multiple data units, such as packets, of a network and within... |
US-7,062,635 |
Processor system and method providing data to selected sub-units in a
processor functional unit A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an... |
US-7,062,526 |
Microprocessor with rounding multiply instructions A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is... |
US-7,062,433 |
Method of speech recognition with compensation for both channel distortion
and background noise A method of speech recognition with compensation is provided by modifying HMM models trained on clean speech with cepstral mean normalization. For all speech... |
US-7,062,430 |
Designing boundary filters for a biorthogonal filter bank A signal processing device includes a biorthogonal filter bank that processes a finite length signal including a left boundary and a right boundary. The... |
US-7,062,304 |
Task based adaptative profiling and debugging A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management... |
US-7,062,244 |
Speed-up mode implementation for direct conversion receiver A speed-up mode control system is operative to generate a speed-up mode signal based on a gain control signal from associated digital circuitry. The speed-up... |
US-7,062,037 |
Generic line impedance matching circuit using decomposed configurable
transfer functions A technique for implementing impedance matching circuits 100 that use the transfer functions of each line impedance model. This technique allows implementation... |
US-7,062,003 |
Self-tuning baud rate generator for UART applications The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data... |
US-7,061,989 |
Fully digital transmitter including a digital band-pass sigma-delta
modulator A digital transmitter (20) that may be advantageously used in a high-frequency transceiver, such as a wireless telephone handset, is disclosed. The transmitter... |