Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: texas instruments
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-6,977,443 |
Substrate for carrying a semiconductor chip and semiconductor device using
same The objective of this invention is to provide a type of substrate for carrying a semiconductor chip that can increase the arrangement density of lands, and a... |
| US-6,977,437 |
Method for forming a void free via A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier... |
| US-6,977,429 |
Manufacturing system and apparatus for balanced product flow with
application to low-stress underfilling of... A system (100) for manufacturing product, in which a first work station (101) is operable to perform a first manufacturing action on the product parts; this... |
| US-6,977,196 |
Micro-electromechanical switch fabricated by simultaneous formation of a
resistor and bottom electrode The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical... |
| US-6,977,191 |
Apparatus for and method of packaging semiconductor devices A carrier and package for plural semiconductor devices includes a member with device-conformal apertures therethrough. A first removable cover is attached to one... |
| US-6,975,980 |
Hierarchical linking module connection to access ports of embedded cores An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports... |
| US-6,975,920 |
In-situ randomization and recording of wafer processing order at process
tools Wafer order is randomized in-situ by use of a separate wafer staging area and randomly shuffling wafers to and from this staging area to shuffle the processing... |
| US-6,975,722 |
Dual echo canceller with fast reflector identification An echo canceller, which includes, receives and sends paths connected to standard telecommunication interfaces, a non adaptive filter with filter reflection... |
| US-6,975,684 |
Dynamic slave frequency selection for improving uplink frequency hopping
wireless communications In wireless communications between a frequency hopping master device (M) and a frequency hopping slave device (S.sub.1), the slave-to-master transmission... |
| US-6,975,629 |
Processing packets based on deadline intervals A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of... |
| US-6,975,473 |
Power efficient overshoot protection during an operating mode transition A system and method provide overshoot protection to facilitate driving a load by output circuitry in response to a transition from a first operating mode to a... |
| US-6,975,354 |
Digital still camera color filter array interpolation system and method Digital Still Camera (DSC) includes separate preview engine, burst mode compression/decompression engine, image pipeline, CCD plus CCD controller, and memory... |
| US-6,975,255 |
Random interleaving dither for sigma-delta analog-to-digital converters A dithering method is provided for sigma-delta converters in a deep-submicron process. The dither is a random interleaving of quantizer thresholds levels. The... |
| US-6,975,170 |
Adaptive amplifier output common mode voltage adjustment The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential... |
| US-6,975,153 |
Low power input with hysteresis circuit and methods therefor A low power input with hysteresis circuit provides input hysteresis (for instance, from supply voltage ranges of 0.8 volt to 5.5 volts), while reducing the... |
| US-6,975,143 |
Static logic design for CMOS A static logic circuit with a pull-up network (155) and a pull-down network (160). The network is fabricated on SOI substrates and the pull-up network comprises... |
| US-6,975,099 |
Efficient frequency compensation for linear voltage regulators The present application describes a frequency compensation scheme for a linear voltage regulator circuit, or its special case, a low-drop out voltage regulator... |
| US-6,974,968 |
Method and apparatus for fabricating self-aligned contacts in an integrated
circuit An integrated circuit includes a substrate with a gate section projecting upwardly between spaced source and drain regions. Side walls project upwardly beyond... |
| US-6,973,934 |
Method for removing particles on semiconductor wafers The purpose of the present invention is to remove minute particles adhered to the surface of semiconductor wafers effectively in the cleaning process of... |
| US-6,973,611 |
Interleaved coder and method Turbo encoder with even-odd bit interleaving for upper and lower component convolutional encoders and symbol-level interleaving after mapping to modulation... |
| US-6,973,337 |
Apparatus for the mobile communication device in low power consumption
using LDO regulator with sleep mode A mobile communications device (50) includes a plurality of LDOs (30) for supplying a stable voltage to various circuits on the device. In a normal mode, the... |
| US-6,973,117 |
Dynamic extension of frequency hopping patterns in wireless communications In a duplex link (40, 60, 90, 116) coupling first and second frequency hopping wireless communication devices, either or both of the frequency hopping patterns... |
| US-6,972,484 |
Circuit structure integrating the power distribution functions of circuits
and leadframes into the chip surface An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are... |
| US-6,972,470 |
Dual metal Schottky diode An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another... |
| US-6,972,448 |
Sub-lithographics opening for back contact or back gate A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in... |
| US-6,970,967 |
Crossbar circuit having a plurality of repeaters forming different repeater
arrangements A crossbar circuit (30, 40, 50, 60, 70, 80, 90, 100) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at... |
| US-6,970,964 |
Using PCMCIA/PCI drivers to control USB ports A filter driver (125) can communicate with the USB stack and controller and with the CardBay, CardBus, and flashmedia stack and controller. This can allow the... |
| US-6,970,951 |
Method and device for providing and external interface using a programmed
configuration bit in flash memory An external interface for a microprocessor system uses a programmed configuration bit to establish the functionality of a computer port, which improves external... |
| US-6,970,528 |
Method and apparatus to measure jitter A method of determining jitter is provided by providing a sample, performing an unwrap of the data and then performing a Fast Fourier Transform (FFT) of the... |
| US-6,970,525 |
High-speed, high granularity baud clock generation A baud clock (15) for use by a serial communication interface (67) is generated by dividing a base clock of the serial communication interface by one of a... |
| US-6,970,495 |
Adjustment of slave frequency hopping pattern to improve channel
measurement opportunities in wireless... The frequency hopping pattern of a first wireless communication device is modified such that each transmission (73) to a second wireless communication device is... |
| US-6,970,440 |
Enhanced performance in frequency hopping wireless communications by
combining frequency dwelling with data... In wireless communications between first and second frequency hopping wireless communication devices, both devices can dwell on a single selected frequency... |
| US-6,970,430 |
Method to measure throughput efficiency of low speed modem relay over
packet network Modem relay provides a local interface to the modem on both ends of a call, demodulates the full duplex data stream, packetizes the bits for transport over an IP... |
| US-6,970,371 |
Reference generator system and methods for reading ferroelectric memory
cells using reduced bitline voltages Methods (200) and systems (108) are provided for reading data from ferroelectric memory cells (106) in which charge is removed from a sense amp input... |
| US-6,970,339 |
Current limit protection scheme for PWM buck converter with synchronous
rectifier A embedded overcurrent protection circuit within the PWM feedback controller (30) of a power converter (100) having an novel current limit detection function... |
| US-6,970,233 |
System and method for custom-polarized photolithography illumination In one embodiment, a system for custom-polarized photolithography illumination includes an illuminator operable to generate an illumination pattern of light, a... |
| US-6,970,150 |
Control timing for spatial light modulator A spatial light modulator clocking method, called fast-clear, which employs embedded clear hardware in the SLM to enable the fast-clear bit to generate... |
| US-6,970,122 |
Integral nonlinearity error correction for interpolating string DAC A segmented string digital-to-analog converter (DAC) comprises least significant bits (LSB subword) interpolation circuitry. The LSB subword interpolation... |
| US-6,970,038 |
Switching scheme to improve linearity and noise in switched capacitor stage
with switched feedback capacitor A switch capacitor amplifier using a "bottom plate sampling" type arrangement in the feedback network to mitigate the reduction in linearity due to feedback... |
| US-6,970,023 |
Modulated transistor gate driver with planar pulse transformer Disclosed are methods and apparatus for isolating and driving a power supply or power amplifier circuit. The circuits and methods provide for using a modulated... |
| US-6,970,005 |
Multiple-chip probe and universal tester contact assemblage A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on one surface a plurality of protruding... |
| US-6,969,979 |
Multiple mode switching regulator having an automatic sensor circuit for
power reduction A switching regulator having a control circuit that automatically senses when a low power mode should be initiated without the use of expensive external... |
| US-6,969,972 |
Architecture for switching between an external and internal power source The present invention comprises a combination of a new circuit topology utilizing microcontroller (202, 302) and a modified logic control circuit which enables... |
| US-6,969,919 |
Semiconductor package production method and semiconductor package A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer... |
| US-6,969,902 |
Integrated circuit having antenna proximity lines coupled to the
semiconductor substrate contacts An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the... |
| US-6,969,901 |
Method and structure for a low voltage CMOS integrated circuit
incorporating higher-voltage devices A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively... |
| US-6,969,880 |
High capacitive density stacked decoupling capacitor structure A capacitive structure (10). The capacitive structure comprises a semiconductor base region (30) having an upper surface, a well (12) formed within the... |
| US-6,969,649 |
Method of manufacturing semiconductor integrated circuit devices having a
memory device with a reduced bit line... A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines... |
| US-6,969,644 |
Versatile system for triple-gated transistors with engineered corners The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate... |
| US-6,969,641 |
Method and system for integrated circuit packaging According to one embodiment of the invention, a method of packaging integrated circuits includes disposing an integrated circuit chip outwardly from a first... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.