Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: texas instruments
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,237,081 |
Secure mode for processors supporting interrupts A digital system is provided with a secure mode (3.sup.rd level of privilege) built in a non-invasive way on a processor system that includes a processor core,... |
| US-7,237,071 |
Embedded symmetric multiprocessor system with arbitration control of
access to shared resources A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors includes a single program... |
| US-7,237,065 |
Configurable cache system depending on instruction type A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the... |
| US-7,237,000 |
Speed of execution of a conditional subtract instruction and increasing
the range of operands over which the... A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of... |
| US-7,236,930 |
Method to extend operating range of joint additive and convolutive
compensating algorithms The operating range of joint additive and convolutive compensating method is extended by enhanced channel estimation procedure that adds SNR-dependent inertia... |
| US-7,236,556 |
Synchronising circuit In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronized with the data... |
| US-7,236,552 |
Data transmission A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for ach... |
| US-7,236,544 |
Enhanced preamble to enable low power detection System and method for enabling the low power detection of a transmitted sequence. A preferred embodiment comprises the replacement of a portion of a preamble... |
| US-7,236,532 |
Method of initializing a communication system with different bandwidth
receivers and transmitters A method of communicating across a channel includes receiving information having a known bandwidth and a known spectrum. The information is preferably in the... |
| US-7,236,511 |
Structured adaptive frequency hopping The invention generally provides a method of intelligent frequency hopping such as in Bluetooth and Home RF networks. The method (100) includes the acts of... |
| US-7,236,396 |
Area efficient implementation of small blocks in an SRAM array An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure... |
| US-7,236,268 |
Adaptive screening in raster image processing of complex pages A method of data processing is described for generating a screened bitmap in an adaptive manner. The page being printed is subdivided into a plurality of smaller... |
| US-7,236,150 |
Transferring data directly between a processor and a spatial light
modulator A method of loading data into a spatial light modulator, in which a software programmable processor stores binary values for the pixels of at least a portion of... |
| US-7,236,055 |
Differential amplifier circuit and method for reducing thermally induced
offsets caused by large differential... An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled... |
| US-7,236,036 |
Apparatus and method for generating pulses An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for... |
| US-7,236,034 |
Self correcting scheme to match pull up and pull down devices The self correcting scheme to match pull up and pull down devices includes: a first comparator for comparing a common mode signal to a high reference limit; a... |
| US-7,236,030 |
Method to implement hysteresis in a MOSFET differential pair input stage A simplified comparator circuit (10) having hysteresis and lower power requirements for its implementation. The circuit (10) includes 2 minimum-sized MOSFETs... |
| US-7,236,021 |
Method of controlling slope and dead time in an integrated output buffer
with inductive load A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive... |
| US-7,236,003 |
H-bridge circuit with shoot through current prevention during power-up The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the... |
| US-7,235,958 |
Apparatus and method to synchronize switching frequencies of multiple
power regulators A power supply has a plurality of switching regulators providing a like plurality of regulated output voltages. The oscillators of the switching regulators are... |
| US-7,235,451 |
Drain extended MOS devices with self-aligned floating region and
fabrication methods therefor Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region... |
| US-7,234,121 |
Method of fabricating an integrated circuit to improve soft error
performance The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error... |
| US-7,234,034 |
Self-clocking memory device A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an... |
| US-7,233,628 |
Data transmission A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each... |
| US-7,233,597 |
High speed parser A high speed parser containing a content addressable memory (CAM) providing select values to multiplexers. The CAM is programmed to implement search rules which... |
| US-7,233,427 |
Display system with clock dropping A display system includes a light source 110 and a spatial light modulator 122 located to receive light from the light source. The spatial light modulator (e.g.,... |
| US-7,233,343 |
Serial printing with multiple torsional hinged MEMS mirrors System and method for operating four resonant torsional hinged mirrors such as torsional hinged MEMS devices at the same oscillating frequency suitable for use... |
| US-7,233,275 |
Analog-to-digital converter with input signal range greater than supply
voltage and extended dynamic range An analog-to-digital converter device capable of measuring inputs beyond a supply voltage including: an N bit analog-to-digital converter powered by a supply... |
| US-7,233,209 |
Integrated preamplifier circuit for detecting a signal current from a
photodiode An integrated preamplifier circuit for detecting a signal current from a photodiode and converting the signal current into an output voltage is provided. The... |
| US-7,233,194 |
CMOS voltage booster circuits This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage... |
| US-7,233,174 |
Dual polarity, high input voltage swing comparator using MOS input
transistors A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential... |
| US-7,233,074 |
Semiconductor device with improved contacts A device with a solder joint made of a copper contact pad (210) of certain area (202) and an alloy layer (301) metallurgically attached to the copper pad across... |
| US-7,233,035 |
Dual work function gate electrodes using doped polysilicon and a metal
silicon germanium compound A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the... |
| US-7,233,015 |
System and method for detecting liquid flow from a nozzle in a
semiconductor processing device A system for detecting liquid flow from a nozzle in a semiconductor processing device includes a first fiber optic sensor, a second fiber optic sensor, and an... |
| US-7,232,768 |
Hydrogen plasma photoresist strip and polymeric residue cleanup process
for low dielectric constant materials A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position... |
| US-7,232,748 |
BARC/resist via etchback process A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O.sub.2/CO. The BARC etch may be used in a via-first dual damascene... |
| US-7,232,744 |
Method for implanting dopants within a substrate by tilting the substrate
relative to the implant source The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a... |
| US-7,232,224 |
Simultaneous color illumination According to one embodiment of the present invention, a method for color illumination for an image display system includes field sequentially operating an array... |
| US-RE39,697 |
Method of making floating-gate memory-cell array with digital logic
transistors A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit... |
| US-7,231,566 |
Initializing an output memory circuit of a scan cell A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is... |
| US-7,231,184 |
Low overhead transmit channel estimation A transmit channel (g.sub.t1, h, g.sub.r2) through which a first wireless communication transceiver is to transmit to a second wireless communication transceiver... |
| US-7,230,868 |
Stable source-coupled sense amplifier An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of... |
| US-7,230,656 |
Sequential color filter A sequential color filter and display system. The sequential color filter comprising: a set of at least three color filters (102). The color filters can be... |
| US-7,230,481 |
System and method for reducing audible artifacts in an audio system An amplifier system can include a biasing amplifier that provides a first amplified signal to a DC blocking element that is connected with a load based on a... |
| US-7,230,473 |
Precise and process-invariant bandgap reference circuit and method A voltage generation circuit generates a reference voltage using a bandgap reference. A countering circuit is included to adaptively counter for any deviations... |
| US-7,230,452 |
Driver circuit A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state... |
| US-7,230,447 |
Fault tolerant selection of die on wafer Integrated circuit die on wafer are electronically selected for testing using circuitry (161, 201, PA1 PA4) provided on the wafer. |
| US-7,230,325 |
Encapsulation for particle entrapment A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents... |
| US-7,229,873 |
Process for manufacturing dual work function metal gates in a
microelectronics device The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS... |
| US-7,229,871 |
Integrated circuit containing polysilicon gate transistors and fully
silicidized metal gate transistors A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.