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| Patent # | Description |
|---|---|
| US-7,116,459 |
Field diode detection of excess light conditions for spatial light
modulator An improved SLM that is capable of detecting when light incident on the SLM exceeds a predetermined threshold. A diode is fabricated around, or within the pixel... |
| US-7,116,261 |
Method and apparatus for accurate inverse-linear voltage/current generator To make use of its full input voltage operating range, an analog-to-digital converter is configured with a switched-capacitor circuit to produce a digital output... |
| US-7,116,239 |
Current sense components failure detection in a multi-phase power system An evaluator (210) having an input (207) for receiving a signal indicative of a channel current sensed via a sensor in a mutlichannel current sharing system, and... |
| US-7,116,172 |
High-swing folded cascode having a novel gain-boost amplifier A circuit topology for gain boosted high-swing folded cascode has been improved to maximize the available dynamic range in applications having low supply voltage... |
| US-7,116,169 |
Driver apparatus and method of operation thereof A driver apparatus comprising a signal switching circuit coupled for receiving an actuation signal and generating a first and a second control signal in response... |
| US-7,116,158 |
Bandgap reference circuit for ultra-low current applications A bandgap reference circuit as may be used in ultra-low current applications is provided. An exemplary bandgap circuit can be configured to generate a positive... |
| US-7,116,139 |
Apparatus and method for controlling operation of a processor device
during startup An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage... |
| US-7,116,113 |
Systems and methods for sense FET calibration Systems, methods and circuits for sense circuit calibration. In one particular case, a system is provided that includes a sense circuit, a calibration circuit,... |
| US-7,116,085 |
DC-DC converter The objective of this invention is to reduce the current flowing through the inductance element in a step-up/step-down DC--DC converter and to control the ripple... |
| US-7,115,530 |
Top surface roughness reduction of high-k dielectric materials using
plasma based processes A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing... |
| US-7,115,467 |
Metal insulator metal (MIM) capacitor fabrication with sidewall barrier
removal aspect A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the... |
| US-7,115,461 |
High permittivity silicate gate dielectric A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device... |
| US-7,114,053 |
Virtual-to-physical address conversion in a secure system In some embodiments, a storage medium comprises application software that performs one or more operations and that directly facilitates the conversion of a... |
| US-7,113,902 |
Data processing condition detector with table lookup In support of data processing emulation, a data processing condition indicated by a predetermined number of digital data processing signals can be detected by... |
| US-7,113,759 |
Controller area network transceiver having capacitive balancing circuit
for improved receiver common-mode rejection A controller area network transceiver and a transmission method for a controller area network provides improved symmetry between its differential output signal... |
| US-7,113,556 |
Reliable decision directed adaptation in a communication system employing
forward error control The present invention provides a method and apparatus for selectively updating an adaptive element in a communications receiver based on a determination that the... |
| US-7,113,543 |
Video encoding Motion compensation as for video compression with motion estimation with either frame mode or field mode by initial prediction of motion mode and when prediction... |
| US-7,113,516 |
Transmit buffer with dynamic size queues A method and apparatus for providing multiple queues that share a single memory buffer. A memory buffer is divided into a plurality of fixed length memory... |
| US-7,113,499 |
Wireless communication A wireless communication transmission channel estimation by initial data exchange to determine calibration factors to apply to tracked channel estimations from... |
| US-7,113,361 |
Retract method to reduce head friction with the disk for a hard disk drive An apparatus, method and system for retracting a read/write head (13) to a landing position of a disk (11) in a disk drive system (10) which includes an actuator... |
| US-7,113,359 |
Impedance-controlled write driver for low power preamp Disclosed are methods and circuits for impedance-controlled write drivers using matched impedance control circuits coupled in parallel with a magnetic write head. |
| US-7,113,302 |
Printer with unified display list and banded display lists A method is provided for generating an image having a plurality of bands. A page description representative of elements of the image is received from an external... |
| US-7,113,226 |
Method for generating a representation of a particular signal among a
plurality of signals representing lines... A method for generating a representation of a particular signal among video signals representing a display, the signals including a first component having a... |
| US-7,113,117 |
Reducing the effect of noise present along with an input signal when
sampling the input signal An aspect of the present invention reduces the effect of any noise present along with an input signal when sampling the input signal by charging each of several... |
| US-7,113,044 |
Precision current mirror and method for voltage to current conversion in
low voltage applications A voltage-to-current conversion circuit includes an error amplifier (12A) which amplifies a voltage difference between the drains of the first (6) and second (7)... |
| US-7,113,039 |
Gain-boosted opamp with capacitor bridge connection The number of compensation capacitors of an opamp may be reduced by connecting the compensation/decoupling capacitor element or elements between the load node... |
| US-7,112,953 |
Method for detecting epitaxial (EPI) induced buried layer shifts in
semiconductor devices The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried... |
| US-7,112,950 |
Integrated circuit for use with an external hall sensor, and hall sensor
module An integrated circuit for use with an external Hall sensor that permits to at least substantially cancel out the temperature drifts of the Hall sensor, as caused... |
| US-7,112,546 |
Method of manufacturing semiconductor devices comprising a deposition tool
cleaning process having a moving... The present invention provides, in one embodiment, a method of manufacturing semiconductor devices. The method comprises transferring one or more substrate into... |
| US-7,112,540 |
Pretreatment for an electroplating process and an electroplating process
in including the pretreatment The present invention provides an electroplating process and a method for manufacturing an integrated circuit. The electroplating process includes, among other... |
| US-7,112,532 |
Process for forming a dual damascene structure The invention describes a method for forming a dual damascene structure. An etch stop layer (150) is formed on a dielectric layer (140). A second dielectric... |
| US-7,112,516 |
Fabrication of abrupt ultra-shallow junctions One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity... |
| US-7,112,497 |
Multi-layer reducible sidewall process The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design... |
| US-7,112,480 |
Method and structure for a low voltage CMOS integrated circuit
incorporating higher-voltage devices A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively... |
| US-7,112,288 |
Methods for inspection sample preparation Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected... |
| US-7,112,286 |
Thin film resistor structure and method of fabricating a thin film
resistor structure A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical... |
| US-7,111,292 |
Apparatus and method for secure program upgrade An appliance includes a memory having at least a hidden partition of memory. The hidden partition of memory operates to store at least a portion of a program... |
| US-7,111,182 |
Thread scheduling mechanisms for processor resource power management A real-time operating system runs on a processor and dynamically manages the power state of individual circuits or resources with the processor. Thus, if a... |
| US-7,111,177 |
System and method for executing tasks according to a selected scenario in
response to probabilistic power... A distributed processing system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power... |
| US-7,110,956 |
Capability predictor A capability predictor that comprises a database 15 of capability of multiple designs is disclosed. The process capability data includes costs, quality, cycle... |
| US-7,110,782 |
Cell search synchronization Cell search synchronization in spread spectrum communications systems using primary and second synchronization codes with symbol partitioning for shorter... |
| US-7,110,732 |
Subsampling RF receiver architecture A subsampling receiver (50, 50', 50'') for converting an RF signal to baseband is disclosed. The subsampling receiver (50, 50', 50'') may be implemented into a... |
| US-7,110,477 |
Gaussian frequency shift keying digital demodulator A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after... |
| US-7,110,445 |
Oversampled clip-shaping The present invention provides an apparatus, system and method of peak-to-average reduction of an oversampled signal for a digital communication system. Peak... |
| US-7,110,432 |
Orthogonal chirp modulation in multipath environments Methods and systems for communication systems are disclosed. Chirp signals generated according to a chirp rate and carrier frequency are used for communication.... |
| US-7,110,370 |
Method and apparatus for coordinating multi-point to point communications
in a multi-tone data transmission system A variety of bidirectional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a... |
| US-7,110,204 |
Process-insensitive write current generation for a HDD preamplifier writer
equipped with parallel output... The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel... |
| US-7,109,902 |
Method and system for sampling a signal According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal... |
| US-7,109,838 |
System for integrating a toroidal inductor in a semiconductor device An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a... |
| US-7,109,812 |
Apparatus and method for presenting a linear capacitive output in response
to a voltage input An apparatus for presenting a substantially linear capacitive output at at least one output locus in response to a voltage input at an input locus, the voltage... |
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