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Patent # Description
US-7,002,506 Providing pipe line ADC with acceptable bit error and power efficiency combination
A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge...
US-7,002,496 All-digital calibration of string DAC linearity using area efficient PWL approximation: eliminating hardware...
A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of...
US-7,002,406 Loop filter for class D amplifiers
A class-D amplifier circuit (30; 30') providing improved open-loop error for base-band frequencies, such as the audio band, is disclosed. The amplifier circuit...
US-7,002,369 Implementing complex clock designs in field programmable devices
An aspect of the present invention simplifies the implementation of complex clock designs in field programmable devices (FPD). To implement a circuit logic...
US-7,002,240 Semiconductor leadframe for staggered board attach
The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities,...
US-7,002,129 Charge detection node with reset feed-through shielding gate
The charge detection device includes a floating diffusion, a reset transistor, a feed through shielding transistor, and a bias tracking voltage reference...
US-7,001,848 Hydrogen plasma photoresist strip and polymeric residue cleanup process for oxygen-sensitive materials
Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor...
US-7,001,821 Method of forming and using a hardmask for forming ferroelectric capacitors in a semiconductor device
Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or...
US-7,000,822 Wire bond integrity test system
An improved bond integrity test system is provided by eliminating the spring loaded wire spool cover which contributes to particulate matter, and by addition of...
US-7,000,478 Combined pressure and temperature transducer
A combined pressure and temperature transducer (10) particularly adapted for high temperature fluids has a sensing element assembly mounted at the tip of a...
US-6,999,981 Circuit for computing the absolute value of complex numbers
An apparatus (100) for computing the absolute value of a complex number includes separate squaring units (110, 115) for the real and imaginary parts. A square...
US-6,999,799 System and method for adaptive deep-sleep slotted operation
A system and method have been provided that permit a mobile station to enter a deep-sleep slotted mode of operation in response to detected patterns of low...
US-6,999,534 Method for mitigating DC offset in a sign bit correlator
A method 10 is provided to mitigate DC offset in a sign bit correlator associated with a packet detection circuit. The input sign pattern is monitored; and if a...
US-6,999,530 Using SISO decoder feedback to produce symbol probabilities for use in wireless communications that utilize...
In a wireless communication receiver (31) of a wireless communication system that utilizes transmit diversity and turbo coding, symbol probabilities (45, 46) are...
US-6,999,508 Multi-channel frequency domain equalizer for radio frequency interference cancellation
A multichannel frequency domain equalizer improves the subchannel signal to noise ratio by canceling correlated noise that is caused by deterministic spreading...
US-6,999,215 Multilayered oscillating functional surface
A multilayered torsional hinged scanning mirror including a hinge layer with a mirror attaching member pivotally supported by torsional hinges. A mirror layer is...
US-6,998,910 Amplifier using delta-sigma modulation
An amplifier and a driver circuit therefor are presented for driving a load according to a system analog input. The amplifier comprises a passive delta-sigma...
US-6,998,904 Circuit and method for turn-on of an internal voltage rail
The circuit and method for turning on an internal voltage rail includes: coupling a first transistor between a power supply node and an internal voltage rail...
US-6,998,898 Programmable front end for a receiving channel
The present invention discloses a circuit used to couple an input signal to an amplifier circuit. The circuit may contain a diode bridge coupled to an adjustable...
US-6,998,799 System and method for improved motor control
A system and method of motor control enable improved motor control by controlling a phase winding to float or enter a high impedance state prior to activating...
US-6,998,297 Wafer level packaging
An integrated circuit package (50) may include an integrated circuit chip (22) having an integrated circuit (14). A lead frame (28) may be opposite the...
US-6,998,275 Hydrogen-less CVD TiN process for FeRAM VIA0 barrier application
The present invention is directed to a method of forming a diffusion barrier layer for a FeRAM capacitor, which includes depositing a chemical vapor deposited...
US-6,998,221 Method for forming a via in a substrate
The present invention provides a method for forming a via (e.g., a trench, via or contact) in a substrate. The method, in one embodiment of the invention,...
US-6,997,192 Control of dissolved gas levels in deionized water
An embodiment of the invention is an apparatus having a cleaning tank 2, a megasonic energy source 3, and an intake pipe 6 where a membrane contactor 9 is...
US-6,996,787 Integrated circuit cells
According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a...
US-6,996,765 Turbo decoder prolog reduction
This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric...
US-6,996,761 IC with protocol selection memory coupled to serial scan path
A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register...
US-6,996,747 Program counter trace stack, access port, and serial scan path
A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor...
US-6,996,735 Apparatus for alignment of data collected from multiple pipe stages with heterogeneous retention policies in an...
A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory...
US-6,996,730 Adjusting voltage supplied to a processor in response to clock frequency
A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit is provided. A request signal is sent to the clock, and in...
US-6,996,683 Cache coherency in a multi-processor system
A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the...
US-6,996,231 Step size convergence control
A method of converging a step size control for an adaptive filter of a communication channel including: (1) initializing a nominal step size value and a penalty...
US-6,996,162 Correlation using only selected chip position samples in a wireless communication system
A method (70) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises a first synchronization...
US-6,996,118 Central office line card with code recognition for increasing data rates over PSTN
A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152)...
US-6,996,091 Central office line card with code recognition for increasing data rates over PSTN
A linecard (175) permits an increased rate connection between a subscriber (15) and a service provider (40) over the PSTN (50) includes an analog interface (152)...
US-6,996,015 First-in first-out memory system with single bit collision detection
An electronic device (10). The device comprises a memory structure (12) structure comprising an integer M of word storage locations. The device further comprises...
US-6,995,810 Method and system for automated convergence and focus verification of projected images
A method and system that objectively measures the convergence and focus of a 2 or 3 spatial light modulator (SLM) projection display. The system uses five (5)...
US-6,995,647 Low current electric motor protector
A low current motor protector (10, 10') has an oblong metal housing (12) defining a switch chamber and formed with an open end. The housing has opposing flange...
US-6,995,624 Oscillator circuit having a copy of the activating component
Oscillator circuit with an LC resonant circuit 1, an activating component 2 connected to the LC resonant circuit 1, which serves to compensate for the losses...
US-6,995,599 Cross-conduction blocked power selection comparison/control circuitry with NTC (negative temperature...
Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array...
US-6,995,598 Level shifter circuit including a set/reset circuit
The present invention discloses a level shifter circuit (20) comprising a serially coupled first device (M3) and second device (M5), a serially coupled third...
US-6,995,587 Low voltage low power bandgap circuit
Disclosed are methods and circuits for providing a bandgap reference in an electronic circuit having a supply voltage and ground. The methods include steps for...
US-6,995,537 Closed-loop control system to mitigate PWM switching noise
One aspect of the present invention provides a motor control system that includes a linear control system operative, in a linear mode, to provide a plurality of...
US-6,995,483 Synchronous buck and boost regulator power reduction circuit using high side sensing
A synchronous DC-DC regulator, adapted to receive a high side pulsed signal and a low side pulsed signal that is substantially the inverse of the high side...
US-6,995,097 Method for thermal nitridation and oxidation of semiconductor surface
An embodiment of the instant invention is a method of forming a dielectric layer on a silicon-containing structure, the method comprising the steps of: providing...
US-6,995,088 Surface treatment of copper to improve interconnect formation
The present invention provides, in one embodiment, a method of forming a copper layer (100) over a semiconductor substrate (105). The method comprises coating a...
US-6,995,042 Method for fabricating preplated nickel/palladium and tin leadframes
A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a...
US-6,995,037 Structure and method of high performance two layer ball grid array substrate
A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an...
US-6,994,544 Wafer scale thermal stress fixture and method
A fixture for supporting a plurality of semiconductor chips during the thermal cycling of the chips, including a fluid-permeable bottom screen, a...
US-6,993,736 Pending bug monitors for efficient processor development and debug
This invention addresses difficult issues encountered in simulations and design verification efforts on complex microprocessor/digital signal processor devices....
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