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Patent # Description
US-6,930,624 Continuous time fourth order delta sigma analog-to-digital converter
A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a...
US-6,930,551 Zero voltage class AB minimal delay output stage and method
A class AB output circuit includes a P-channel pullup transistor (M13) having a source coupled to a supply voltage, a drain coupled to an output(10), a gate...
US-6,930,548 Method and system for improving amplifier efficiency
One aspect of the invention is an amplifier (10), comprising an input stage amplifier (20) coupled to an output node (81). The amplifier (10) further comprises a...
US-6,930,531 Circuit and method to compensate for RMR variations and for shunt resistance across RMR in an open loop current...
The present invention discloses a circuit (10) adapted to compensate for RMR variations and shunt resistance across the RMR comprising a first current source...
US-6,930,049 Endpoint control for small open area by RF source parameter Vdc
A method of detecting endpoint of a plasma etching system that measures the DC voltage drop across both the sheath and the film being etched. When the film is...
US-6,930,028 Antireflective structure and method
The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist...
US-6,930,018 Shallow trench isolation structure and method
Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments...
US-6,930,007 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility...
US-6,930,005 Low cost fabrication method for high voltage, high drain current MOS transistor
A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage....
US-6,929,971 Semiconductor device and its manufacturing method
Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor...
US-6,929,699 Gas injectors for a vertical furnace used in semiconductor processing
Improved long gas injectors for a vertical furnace used in semiconductor wafer processing are useful to minimize particulate contamination in the wafer...
US-6,928,850 Method and tooling for z-axis offset of lead frames
A method and apparatus for enabling z-axis offset of narrow metal ties straps in lead frames used for packaging integrated circuits to prevent bowing or...
US-6,928,641 Method and system for far branch and call instructions
The present invention provides a method for far branch and call instructions. The present invention includes the link-time modification of object code generated...
US-6,928,569 Automatic output delay timing adjustment for programmable glitch filter
A method for application in a data interface controller receiving asynchronous input data at predetermined one of a plurality of input bit frequencies, wherein...
US-6,928,516 Image data processing system and method with image data organization into tile cache memory
An image data processing system and method are disclosed in which image data is organized for fast and efficient transfer of image data to and from an image...
US-6,928,403 Automatic detection of connectivity between an emulator and a target device
Connectivity between an emulation controller and a plurality of target devices can be automatically detected. After the target devices (Chip1, ChipN) and the...
US-6,928,376 Apparatus and methods for ferroelectric ram fatigue testing
Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric...
US-6,928,039 Method and apparatus for the reduction of power consumption in a compact disc player
A method and apparatus for playing compressed audio compact discs in a CD player is provided in which compressed audio data is cached in the local memory of the...
US-6,928,011 Electrical fuse control of memory slowdown
Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional...
US-6,927,933 Apparatus configured for applying write signals for driving a write head and method for configuring
An apparatus configured according to characteristics for driving a write head to write to a memory device includes: (a) a current directing circuit directing a...
US-6,927,719 Segmented, current-mode digital-to-analog converter
A segmented current mode DAC (200) is disclosed herein having a current matching circuit (260) that compensates for the current mismatch produced by the...
US-6,927,632 Low distortion compression amplifier
A low distortion compression amplifier comprising an amplifier circuit having an input and an output, wherein an input signal is received at the input and...
US-6,927,624 Method and circuit for improving control of trimming procedure
A method and circuit is provided for improving the control of the trimming procedure for various devices without the need for additional dedicated control pins....
US-6,927,493 Sealing and protecting integrated circuit bonding pads
A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and...
US-6,927,428 Lateral heterojunction bipolar transistor
A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20),...
US-6,927,174 Site-specific method for large area uniform thickness plan view transmission electron microscopy sample preparation
A method for preparing a sample includes separating a portion of substrate from a sample, performing focused ion beam milling, and removing additional sample...
US-6,927,159 Methods for providing improved layer adhesion in a semiconductor device
According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a...
US-6,927,137 Forming a retrograde well in a transistor to enhance performance of the transistor
A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the...
US-6,927,106 Methods for fabricating a triple-gate MOSFET transistor
Fabrication methods are presented in which a semiconductor body is deposited in a cavity of a temporary form structure above a semiconductor starting structure....
US-6,927,081 Method of inkless wafer blind assembly
A method of blind assembly processing a wafer by pick and place equipment is described. This method includes determining the wafer diameter or radius and...
US-6,926,150 Protective interleaf for stacked wafer shipping
A package includes a first and a second wafer stored therein in a stacked configuration. The first wafer has interconnection conductor material portions...
US-6,925,634 Method for maintaining cache coherency in software in a shared memory system
The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software...
US-6,925,521 Scheme for implementing breakpoints for on-chip ROM code patching
The present invention relates to a system and a method for preventing address conflicts when establishing breakpoints and applying one or more patches to code...
US-6,925,408 Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components
A mixed-signal core designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby,...
US-6,925,171 Universal impedance matching network for the subscriber line integrated circuits
A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for...
US-6,925,025 SRAM device and a method of powering-down the same
An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array, (2) peripheral circuitry coupled to...
US-6,925,010 Static random access memory device having decreased sensitivity to variations in channel physical characteristics
A static random access memory (SRAM) device and a method of manufacturing the same. In one embodiment, the SRAM device includes: (1) a first bias voltage contact...
US-6,924,756 Method and system for processing a digital signal
Processing signals to record media information includes receiving an analog signal at an analog-to-digital converter, where the analog signal includes media...
US-6,924,681 Efficient pulse amplitude modulation transmit modulation
Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408...
US-6,924,672 CMOS comparator output stage and method
A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first...
US-6,924,633 Pulse width modulation controller with double pulse immunity
A pulse width modulation (PWM) controller includes a shutter circuit interposed between a PWM modulator and a driver circuit. The shutter circuit receives a raw...
US-6,924,239 Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using "spike"...
The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein...
US-6,924,208 Dual mask capacitor for integrated circuits
An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor...
US-6,922,829 Method of generating profile-optimized code
A method of generating profiled optimized code using user interface (17) that allows a user to visually understand, inspect, and manipulate a compiled...
US-6,922,735 Management of co-processor information by integrating non-program information with program information
A system including a host processor (11) operating in combination with one or more co-processors (13) is disclosed. In this system, a file storage facility (17)...
US-6,922,710 Hand-held calculator with problems and operations linked lists
A hand-held calculator programmed to teach mathematics in a manner which emulates traditional step-by-step teacher-student teaching methods and shows the...
US-6,922,483 Methods for measuring DMD low frequency spatial uniformity
Methods for measuring the low spatial reflectivity uniformity of a DMD spatial light modulator. These methods are unique since they compensate for the...
US-6,922,470 Hybrid DC-feed controller for a subscriber line interface circuit
A method and apparatus in a DC-feed controller for controlling a subscriber line interface circuit controlling voltage (alternately, current) on a telephone line...
US-6,922,448 Upstream power back-off
The present invention provides a system and method of an upstream power back-off in a very high rate Digital Subscriber Line (VDSL) system. The method is based...
US-6,922,407 HomePNA 10M8 compliant transceiver
The present invention provides a method and system of transceiving a data signal in a HomePNA type network. The transceiver enables digital signal processing of...
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