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Patent # Description
US-6,943,721 Charge-coupled amplifier and converter with matched offsets
An linear optical sensor charged-coupled topology using single-stage inverting charge-coupled amplifier driving an analog-to-digital converter which uses the...
US-6,943,717 Sigma delta class D architecture which corrects for power supply, load and H-bridge errors
A sigma delta class D device that uses a low pass filter to smooth the output waveform and eliminate high frequency switching noise from the feedback value...
US-6,943,573 System and method for site-to-site yield comparison while testing integrated circuit dies
Disclosed herein are systems and methods for testing the functionality of a plurality of integrated circuit dies formed in a plurality of rows on a semiconductor...
US-6,943,539 Electricity meter with multiple gains signal to an A/D converter
An auto-ranging electricity meter circuit having multiple current signal paths. Each of the current signal paths are amplified by a different amount of gain, and...
US-6,941,576 System and methods for home network communications
A system that permits use of existing cable TV wiring for home networking is disclosed. Because of the presence of splitters, notch filters, and other components...
US-6,941,530 Method of cross-mapping integrated circuit design formats
A method of cross-mapping integrated circuit ("IC") elements nets in a IC and/or directing a probe to points on an IC to achieve minimal interference from...
US-6,941,242 Versatile system for variance-based data analysis
The present invention defines a versatile system for analyzing accuracy of industrial measurement data. The system of the present invention compiles measurements...
US-6,941,232 Method and apparatus for performing multi-site integrated circuit device testing
Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the...
US-6,940,937 Scalable high-speed precision frequency and phase synthesis
A clock synthesis circuit (22) including a phase-locked loop (25) and one or more frequency synthesis circuits (27; 77; 227; 237) is disclosed. A disclosed...
US-6,940,930 Automatic burst mode I/Q gain and I/Q phase calibration using packet based-fixed correction coefficients
A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator and an IQ balancer. The IQ...
US-6,940,675 Efficient hard disk drive energy recovery circuit and method and a hard disk drive incorporating the same
A hard disk drive energy recovery circuit, a method of recovering energy from a motor of a hard disk drive and a hard disk drive. In one embodiment, the hard...
US-6,940,619 Polynomial based multi-level screening
This invention is a computer implemented method of approximating a gray scale tone with a more limited range image producer. One of a plurality of tone curves is...
US-6,940,548 Analog optical black clamping circuit for a charge coupled device having wide programmable gain range
An image processing apparatus (200) for a charge coupled device including analog front end circuitry having optical black and offset correction, whereby the...
US-6,940,438 Method and circuit for reducing quantizer input/output swing in a sigma-delta modulator
Disclosed is a circuit and method for reducing output swing in a sigma delta modulator. The quantizer output swing reduction circuit and method of the present...
US-6,940,436 Analog-to-digital conversion system with second order noise shaping and a single amplifier
A analog-to-digital converters and second order noise shaping systems are presented for providing a noise shaped analog feedback signal to a A/D converter in an...
US-6,940,429 Method of context based adaptive binary arithmetic encoding with decoupled range re-normalization and bit insertion
This invention increases the available instruction level parallelism (IPC) of CABAC encoding by decoupling the re-normalization loop and the bit-insertion task...
US-6,940,342 Method and apparatus for exponential gain variations with a linearly varying input code
A programmable gain amplifier using metal-oxide-semiconductor (MOS) devices to approximate exponential gain characteristic with linear control signals is...
US-6,940,337 Load sensing voltage regulator for PLL/DLL architectures
An apparatus includes a voltage regulator operable to regulate a supply voltage to an on-chip module having an operational current, draw a supply current, and...
US-6,940,336 Voltage regulator with switch-on protection circuit
Voltage regulator with an output transistor MP1, including a first PMOS FET, whereby the input voltage Vdd of the voltage regulator is applied to the source of...
US-6,940,305 Low leakage Ioff and overvoltage Ioz circuit
A blocking circuit technique achieves very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance. The...
US-6,940,275 Magnetic position sensor apparatus and method
A magnetic position sensor has a stator (16', 36, 52) formed of magnetic material and a pair of magnets (14a, 14b; 34a, 34b; 54a, 54b; 64a, 64b) rotatably...
US-6,940,167 Variable cross-section plated mushroom with stud for bumping
An improved bump fabrication process is described that produces a larger diameter/taller solder ball than with a standard mushroom by forming an elongated...
US-6,940,137 Semiconductor device having an angled compensation implant and method of manufacture therefor
The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing...
US-6,940,131 MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication
The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An...
US-6,939,816 Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface
The instant invention is a method for forming a smooth interface between the upper surface of a silicon substrate and a dielectric layer. The invention comprises...
US-6,939,795 Selective dry etching of tantalum and tantalum nitride
The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in ...
US-6,939,736 Ideal operational amplifier layout techniques for reducing package stress and configurations therefor
A method of reducing package stress includes placing matched components of an op-amp substantially in a region of a die having the least stress gradients. The...
US-6,938,060 Apparatus and method for graphically displaying a vector simultaneously along with the numerical values of its...
A handheld computing device (40) comprises a software application adapted to provide instructions to graphically display a vector on a display screen (48)...
US-6,937,916 Automatic recognition of locator die in partial wafermap process
An off-line partial wafer scanner system is disclosed that resolves partial wafermap related issues that result holt-lot in semiconductor assembly. The system...
US-6,937,651 Method and apparatus for compressing image information
A system (10) includes an image detector (12) which is a video camera, and which detects and outputs a succession of video images of a selected subject. A...
US-6,937,623 Method and apparatus for coordinating multi-point to point communications in a multi-tone data transmission system
A variety of bi-directional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a...
US-6,937,382 Active border pixels for digital micromirror device
A method of ensuring that border pixels of a micromirror device are set to the "off" position. The method is typically performed at the factory, during...
US-6,937,180 Code-controlled voltage divider
A code-controlled voltage divider (20) is disclosed. The voltage divider (20) includes an upper portion with a resistor (22) and a dummy switching transistors...
US-6,937,174 Sampling/holding method and circuit
The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple...
US-6,936,919 Heatsink-substrate-spacer structure for an integrated-circuit package
A packaged integrated circuit that includes a substrate 310; a chip 300 mounted on the substrate; and a heatsink 350 mounted on the chip. The heatsink has a...
US-6,936,508 Metal gate MOS transistors and methods for making the same
Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate...
US-6,934,930 Generating an optical model for lens aberrations
Generating an optical model includes receiving lens aberration data associated with a wafer response to lens aberrations. Aberration functions are selected and...
US-6,934,820 Traffic controller using priority and burst control for reducing access latency
A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for...
US-6,934,672 Control loop status maintainer for temporarily opened control loops
A system provides primary and alternate control circuits to a controlled system through an output port. A monitoring circuit that monitors a parameter of the...
US-6,934,417 Transcoding scheme for assistance in image transformations
This invention proposes to transcode the compressed image, that may be in the JPEG format for example, to an intermediate format that allows pseudo-random...
US-6,934,343 Computing the full path metric in viterbi decoding
By utilizing an additional counter and monitoring the maximum state metric at each stage, only forward progressing modulo wrap-arounds will occur and these can...
US-6,934,136 ESD protection of noise decoupling capacitors
Electrostatic discharge protection devices formed at a face of a semiconductor substrate, integrated with a component sensitive to electrostatic discharge,...
US-6,933,970 Digital still camera system and method
An interpolation for a Bayer pattern color-filtered array with edge enhancement by clamping green interpolation values.
US-6,933,874 Applying desired voltage at a node
To apply a desired voltage at a node driving a load impedance, a voltage source providing the desired voltage is connected to the node. In addition, a current...
US-6,933,868 Testing of mixed signal integrated circuits generating analog signals from digital data elements
Testing of a mixed signal integrated circuit (IC) potentially in the form of a die using a tested/calibrated integrated circuit. In an embodiment, the mixed...
US-6,933,784 Output stage for high gain and low distortion operational amplifier
A class-AB MOS output stage that provides higher gain and significantly lower distortion. The class-AB MOS output stage includes a PMOS output transistor and an...
US-6,933,759 Systems and methods of performing duty cycle control
The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections...
US-6,933,741 Electrostatic discharge testers for undistorted human-body-model and machine-model characteristics
An equipment (400) for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator (401) and an on/off...
US-6,933,731 Method and system for determining transistor degradation mechanisms
According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay...
US-6,933,567 Substrate pump ESD protection for silicon-on-insulator technologies
An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has...
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