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Patent # Description
US-6,985,002 System and method for input/output induced latch up detection
The present invention is directed to a system and method of testing an integrated circuit (IC) device for potential latch-up. The system has a power supply...
US-6,985,001 Testing ICs with distributor, collector, and parallel scan paths
An integrated circuit (70) having parallel scan paths (824 842, 924 942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944)...
US-6,984,857 Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating...
Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of...
US-6,984,580 Dual damascene pattern liner
An embodiment of the invention is a dual damascene layer 13 of an integrated circuit 2 containing a dual damascene pattern liner 21. Another embodiment of the...
US-6,984,152 Multifunction passive socket for flash media cards
The present invention enables the use of a single passive socket for multiple types of flash media cards. The present invention provides this by implementing...
US-6,983,450 User configurable operating system
An operating system preferably for use with a digital signal processing target is disclosed which minimizes time and space requirements on the target DSP chip....
US-6,983,441 Embedding a JTAG host controller into an FPGA design
A method for embedding a Joint Test Action Group (JTAG) standard IEEE 1149.1 host controller into a field programmable gate array (FPGA) for platform development...
US-6,983,346 Reducing tag-ram accesses and accelerating cache operation during cache miss
This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache...
US-6,983,298 Method and apparatus for linear interpolation using gradient tables
This invention is a method and apparatus for interpolation which enables simpler and cost efficient implementation in hardware or software. A function table...
US-6,983,297 Shifting an operand left or right while minimizing the number of multiplexor stages
A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with...
US-6,983,032 Digital timing recovery method for communication receivers
The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network....
US-6,982,976 Datapipe routing bridge
The datapipe routing bridge is composed of three building blocks, transmitter, bridge and receiver. The bridge component provides high levels of connectivity...
US-6,982,941 Mirror detection signal generator
An amplitude variation detection circuit that can reliably detect the mirror portion independently of the type of optical recording medium, as well as a type of...
US-6,982,915 SRAM with temperature-dependent voltage control in sleep mode
An electronic device (10), comprising a plurality of data storage cells (12), collectively operable in a data access mode and separately in a sleep mode. The...
US-6,982,694 Source driver
A display device module that can supply high-speed signals with low distortion and drive high-load signal lines at high speed. A switch unit rearranges multiple...
US-6,982,662 Method and apparatus for efficient conversion of signals using look-up table
An apparatus and method for conversion of direct stream digital (DSD) signal samples to pulse code modulated (PCM) signal samples using a look-up table. The...
US-6,982,627 Low power regulated amplifier for a transponder
A transponder (1) comprising an antenna (4), a demodulator (5) and a signal processing circuit (6) which converts a modulated signal received via the antenna (4)...
US-6,982,615 System and method for threaded plunger assembly
A system and method for a plunger assembly includes a tuning slug with a bore in the stem, a tuning screw rotatably disposed in the stem, and a coupling assembly...
US-6,982,610 Termination impedance tuning circuit
An impedance adjustment system comprising current source, a first series and a second series connected string of predetermined number of resistors, a first and...
US-6,982,588 Inverse function method for semiconductor mixer linearity enhancement
The mixer circuit includes a differential rf input driver; a differential local oscillator input circuit coupled to the differential rf input driver; a...
US-6,982,448 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same
Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (C.sub.FE) from hydrogen diffusion in semiconductor devices (102),...
US-6,982,400 Electrical heater apparatus
A self retaining crankcase heater (10) has a tubular casing (12) of relatively flexible, thermally conductive material in which is received a PTC element (16),...
US-6,982,377 Time-scale modification of music signals based on polyphase filterbanks and constrained time-domain processing
A time scale modification method employs separate bands obtained through an analysis polyphase filter bank with separate time-scale modification processing for...
US-6,981,204 Programmable glitch filter for an asynchronous data communication interface
An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels...
US-6,981,190 Controlling the content of specific desired memory elements when testing integrated circuits using sequential...
A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test...
US-6,981,178 Separation of debug windows by IDS bit
A central processing unit that enables real time interrupts during a debug halt stores an interrupt during debug bit corresponding to the return address upon...
US-6,981,130 Forwarding the results of operations to dependent instructions more quickly via multiplexers working in parallel
Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective ...
US-6,980,952 Source normalization training for HMM modeling of speech
A maximum likelihood (ML) linear regression (LR) solution to environment normalization is provided where the environment is modeled as a hidden (non-observable)...
US-6,980,950 Automatic utterance detector with high noise immunity
An utterance detector for speech recognition is described. The detector consists of two components. The first part makes a speech/non-speech decision for each...
US-6,980,588 Apparatus for handling high speed data communication signals and method for manufacture thereof
An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at...
US-6,980,459 Non-volatile SRAM
A SRAM cell wherein the pull up load of the cell is inherent ferroelectric leakage. The power down writeback may include boosting the word line. The power down...
US-6,980,407 Arc detection apparatus and method
Current flowing through a load is monitored by a transformer (Tr1) having a small mutual inductance. The secondary coil is shorted through a rectifier circuit to...
US-6,980,144 Method for reducing DAC resolution in multi-bit sigma delta analog-to digital converter (ADC)
A method for reducing the resolution of a digital-to-analog converter in a multi-bit sigma-delta ADC is described. With the addition of digital sigma-delta...
US-6,980,055 CMOS differential buffer circuit
The present invention pertains to a MOS type differential buffer circuit. The buffer proposed herein utilizes capacitive coupling to apply small AC signals to an...
US-6,979,908 Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements
A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a...
US-6,979,899 System and method for high performance heat sink for multiple chip devices
A custom-molded heat sink corresponds to an individual substrate and includes a heat sink lid having at least one cavity corresponding to at least one die...
US-6,979,788 Electrical switch system responsive to gear selection of vehicular transmission
An electrical switch system (10) for use with a motor vehicle transmission has a movable contact assembly (16) mounted on an insulative base member (14) in turn...
US-6,979,648 Method for BARC over-etch time adjust with real-time process feedback
A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The...
US-6,979,647 Method for chemical etch control of noble metals in the presence of less noble metals
A method for preparing a bonding pad on an integrated circuit wafer by the steps of depositing a conductive seed layer (104) on the bonding pad; depositing a...
US-6,979,637 Method and structure for controlling surface properties of dielectric layers in a thin film component for...
A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming...
US-6,979,623 Method for fabricating split gate transistor device having high-k dielectrics
Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses...
US-6,979,615 System and method for forming a semiconductor with an analog capacitor using fewer structure steps
A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the...
US-6,978,389 Variable clocking in an embedded symmetric multiprocessor system
In multiprocessor systems the task of holding power dissipation to its lowest possible level is challenging. This invention permits reduced power dissipation by...
US-6,978,387 Hold time latch with decreased percharge node voltage leakage
A dynamic logic hold time latch (20). The latch comprises a first phase circuit (12') operable in a precharge phase and an evaluate phase and a second phase...
US-6,977,910 Power control with space time transmit diversity
A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a...
US-6,977,691 System for nonlinear viewing of television show segments
A system for nonlinear viewing of television show segments is provided by transmitting a main signal and an ancillary signal. The ancillary signal is a short...
US-6,977,605 Dummy delay line based DLL and method for clocking in pipeline ADC
A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay...
US-6,977,547 Minimizing changes in the amplification factor of an amplification circuit during operation
A resistor (or a component with impedance that does not change) is provided across the output of an amplifier, which minimizes the changes in the amplification...
US-6,977,542 Adjusting the trans-conductance of a filter
A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having...
US-6,977,488 DC-DC converter
A DC--DC converter can supply a stable output voltage from an input voltage with the power supply voltage varying along with the supply of the power and can...
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