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Patent # Description
US-6,937,180 Code-controlled voltage divider
A code-controlled voltage divider (20) is disclosed. The voltage divider (20) includes an upper portion with a resistor (22) and a dummy switching transistors...
US-6,937,174 Sampling/holding method and circuit
The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple...
US-6,936,919 Heatsink-substrate-spacer structure for an integrated-circuit package
A packaged integrated circuit that includes a substrate 310; a chip 300 mounted on the substrate; and a heatsink 350 mounted on the chip. The heatsink has a...
US-6,936,508 Metal gate MOS transistors and methods for making the same
Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate...
US-6,934,930 Generating an optical model for lens aberrations
Generating an optical model includes receiving lens aberration data associated with a wafer response to lens aberrations. Aberration functions are selected and...
US-6,934,820 Traffic controller using priority and burst control for reducing access latency
A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for...
US-6,934,672 Control loop status maintainer for temporarily opened control loops
A system provides primary and alternate control circuits to a controlled system through an output port. A monitoring circuit that monitors a parameter of the...
US-6,934,417 Transcoding scheme for assistance in image transformations
This invention proposes to transcode the compressed image, that may be in the JPEG format for example, to an intermediate format that allows pseudo-random...
US-6,934,343 Computing the full path metric in viterbi decoding
By utilizing an additional counter and monitoring the maximum state metric at each stage, only forward progressing modulo wrap-arounds will occur and these can...
US-6,934,136 ESD protection of noise decoupling capacitors
Electrostatic discharge protection devices formed at a face of a semiconductor substrate, integrated with a component sensitive to electrostatic discharge,...
US-6,933,970 Digital still camera system and method
An interpolation for a Bayer pattern color-filtered array with edge enhancement by clamping green interpolation values.
US-6,933,874 Applying desired voltage at a node
To apply a desired voltage at a node driving a load impedance, a voltage source providing the desired voltage is connected to the node. In addition, a current...
US-6,933,868 Testing of mixed signal integrated circuits generating analog signals from digital data elements
Testing of a mixed signal integrated circuit (IC) potentially in the form of a die using a tested/calibrated integrated circuit. In an embodiment, the mixed...
US-6,933,784 Output stage for high gain and low distortion operational amplifier
A class-AB MOS output stage that provides higher gain and significantly lower distortion. The class-AB MOS output stage includes a PMOS output transistor and an...
US-6,933,759 Systems and methods of performing duty cycle control
The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections...
US-6,933,741 Electrostatic discharge testers for undistorted human-body-model and machine-model characteristics
An equipment (400) for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator (401) and an on/off...
US-6,933,731 Method and system for determining transistor degradation mechanisms
According to one embodiment, a method for isolating degradation mechanisms in transistors includes providing a ring oscillator having a plurality of delay...
US-6,933,567 Substrate pump ESD protection for silicon-on-insulator technologies
An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has...
US-6,933,248 Method for transistor gate dielectric layer with uniform nitrogen concentration
The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating...
US-6,933,203 Methods for improving well to well isolation
Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted...
US-6,933,177 Aluminum leadframes for semiconductor devices and method of fabrication
A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of...
US-6,933,173 Method and system for flip chip packaging
According to one embodiment of the invention, a method of packaging flip chips includes providing a plurality of flip chips and a panel, forming a plurality of...
US-6,932,915 System and method for integrated oxide removal and processing of a semiconductor wafer
An integrated oxide removal and processing system (10) includes a process module (30) that may intentionally add at least one film layer to a single ...
US-6,931,643 Interrupt throttling for inter-processor communications
Implementation of communication between data processors includes a first task (A) running on a first data processor (11) determining that communication is...
US-6,931,636 Multiprocessor emulation support using dynamic linking
A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system...
US-6,931,243 Fully integrated low noise multi-loop synthesizer with fine frequency resolution for HDD read channel and RF...
A low noise multi-loop radio frequency synthesizer receives an input reference signal having a frequency f.sub.R, into a fine tune PLL and a coarse tune PLL. The...
US-6,931,051 Frequency hopping wireless communication system with filtered adaptive slicer
A wireless communication network comprising a wireless receiver. The wireless receiver comprises at least a first antenna for receiving packets, wherein each of...
US-6,931,012 ATM processor for switching in an ATM system
The present invention provides an apparatus and system for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture...
US-6,930,983 Integrated circuits, systems, apparatus, packets and processes utilizing path diversity for media over packet...
In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer...
US-6,930,953 Self-timed strobe generator and method for use with multi-strobe random access memories to increase memory...
A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a...
US-6,930,689 Hardware extensions for image and video processing
A processing device (200) includes three hardware extensions: a motion estimation extension 202, a pixel interpolation extension 204 and a DCT/iDCT extension...
US-6,930,637 Method and apparatus for high resolution tracking via mono-pulse beam-forming in a communication system
Method and apparatus for high resolution tracking via mono-pulse beam-forming in a communication system in which the capacity and range of mobile or fixed...
US-6,930,624 Continuous time fourth order delta sigma analog-to-digital converter
A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a...
US-6,930,551 Zero voltage class AB minimal delay output stage and method
A class AB output circuit includes a P-channel pullup transistor (M13) having a source coupled to a supply voltage, a drain coupled to an output(10), a gate...
US-6,930,548 Method and system for improving amplifier efficiency
One aspect of the invention is an amplifier (10), comprising an input stage amplifier (20) coupled to an output node (81). The amplifier (10) further comprises a...
US-6,930,531 Circuit and method to compensate for RMR variations and for shunt resistance across RMR in an open loop current...
The present invention discloses a circuit (10) adapted to compensate for RMR variations and shunt resistance across the RMR comprising a first current source...
US-6,930,049 Endpoint control for small open area by RF source parameter Vdc
A method of detecting endpoint of a plasma etching system that measures the DC voltage drop across both the sheath and the film being etched. When the film is...
US-6,930,028 Antireflective structure and method
The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist...
US-6,930,018 Shallow trench isolation structure and method
Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments...
US-6,930,007 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility...
US-6,930,005 Low cost fabrication method for high voltage, high drain current MOS transistor
A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage....
US-6,929,971 Semiconductor device and its manufacturing method
Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor...
US-6,929,699 Gas injectors for a vertical furnace used in semiconductor processing
Improved long gas injectors for a vertical furnace used in semiconductor wafer processing are useful to minimize particulate contamination in the wafer...
US-6,928,850 Method and tooling for z-axis offset of lead frames
A method and apparatus for enabling z-axis offset of narrow metal ties straps in lead frames used for packaging integrated circuits to prevent bowing or...
US-6,928,641 Method and system for far branch and call instructions
The present invention provides a method for far branch and call instructions. The present invention includes the link-time modification of object code generated...
US-6,928,569 Automatic output delay timing adjustment for programmable glitch filter
A method for application in a data interface controller receiving asynchronous input data at predetermined one of a plurality of input bit frequencies, wherein...
US-6,928,516 Image data processing system and method with image data organization into tile cache memory
An image data processing system and method are disclosed in which image data is organized for fast and efficient transfer of image data to and from an image...
US-6,928,403 Automatic detection of connectivity between an emulator and a target device
Connectivity between an emulation controller and a plurality of target devices can be automatically detected. After the target devices (Chip1, ChipN) and the...
US-6,928,376 Apparatus and methods for ferroelectric ram fatigue testing
Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric...
US-6,928,039 Method and apparatus for the reduction of power consumption in a compact disc player
A method and apparatus for playing compressed audio compact discs in a CD player is provided in which compressed audio data is cached in the local memory of the...
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