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Tilt-in-place alignment system and method
Disclosed is a mounting system and method in which symmetrical springs are used about a collar in a gimbal system to capture an assembly of a ball and an optical...
Reduction or moire effect in pixelated rear-projection displays
An apparatus and method for reducing the moire effect in rear-projection displays by rotating the dark-stripe structure (711, 712) in the screen (71) 45.+-.15...
Reducing time to measure constraint parameters of components in an
Reducing the time required to measure constraint parameters (setup time, hold time and pulse width) of components in integrated circuits. For example, the delay...
Using write request queue to prevent bottlenecking on slow ports in
transfer controller with hub and ports...
A data transfer technique between a source port and a destination port of a transfer controller with plural ports. In response to a data transfer request (401),...
Method requesting and paying for download digital radio content
The user receives a digital radio transmission through a digital receiver and transmits a request to download selected content from this transmission to a...
ADSL front-end in a low voltage process that accommodates large line
The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse...
Method and apparatus for spread spectrum interference cancellation
The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator,...
Efficient equalization for detection of symbols in digital burst
The detection of symbols in digital burst transmissions is improved by an equalizer (30) that initializes the values of only a subset of its filter coefficients...
Shielded planar capacitor
A shielded planar capacitor structure (202) is discussed, formed within a Faraday cage (210) in an integrated circuit device (200). The capacitor structure (202)...
Method of expanding high-speed serial video data providing compatibility
with a class of DVI receivers
A method of expanding data to a high-speed serial video link in such a way that it is invisible to existing receivers and such that auxiliary data, i.e. audio...
Digitally-controlled oscillator with switched-capacitor frequency selection
A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The...
Calibrated fully differential RC filter
A calibrated RC filter (4) includes a fully differential calibration circuit (10) and finite state machine (8) for determining processing variations in the...
Regulated cascode current source with wide output swing
System for a current source with enhanced output impedance. A preferred embodiment comprises a cascode current source arranged in a current mirror configuration...
System for improving thermal stability of copper damascene structure
Disclosed is a system for fabricating a semiconductor device (100). An interconnect structure (110) is formed on the semiconductor device (100) and a cap (112)...
Integrated circuit and method
A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with...
Processor having real-time power conservation and thermal management
A real-time power conservation and thermal management apparatus and method for portable computers employs a monitor (40) to determine whether a CPU may rest...
Dynamic hardware control for energy management systems using task
A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management...
Time division multiplex data recovery system using close loop phase and
delay locked loop
A time division multiplex data recovery system using a closed-loop phase lock loop (PLL) and delay locked loop (DLL) is disclosed. In other words, one closed...
Enhanced viterbi decoder for wireless applications
A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric...
ESD protection with uniform substrate bias
Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry...
Torsionally hinged devices with support anchors
A functional surface, such as a reflective surface, is supported by a pair of torsional hinges for pivoting about a first axis which in turn is supported by a...
Modulo addressing for look up table screening for printing files in a page
This invention involves approximating a gray scale tone with a more limited range image producer, a process known as screening. This invention reduces the time...
Automatic detection, selection and configuration of clock oscillator
Oscillator circuitry on an integrated circuit automatically detects the presence or absence of an external resistor which is used to bias and set the frequency...
Method of testing an integrated circuit and an integrated circuit test
A method of testing an Integrated Circuit (IC) and an IC test apparatus is provided. In one embodiment, the method of testing includes (1) applying a voltage to...
Direct attach chip scale package
A reliable, chip scale or flip chip semiconductor device which can be directly attached to a PC board without the use of an underfill material to absorb stress...
Multilayer integrated circuit copper plateable barriers
A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100)...
BARC etch comprising a selective etch chemistry and a high polymerizing gas
for CD control
A BARC etch comprises a selective etch chemistry in combination with a high-polymerizing gas for CD control. The BARC etch may be used in a via-first dual...
LDMOS transistors and methods for making the same
LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between...
Method for controlling wire balls in electronic bonding
A method for forming a substantially spherical free air ball on a fine non-oxidizable wire in a computerized bonder, which has a computerized flame-off (EFO)...
Simplifying integrated circuits with a common communications bus
When integrating a peripheral, it is common practice to use a fully custom design. Custom designs typically optimize performance, size, and energy usage....
IC with cache bit memory in series with scan segment
Low power delay test capabilities in Scan and Scan-BIST architectures occur by inserting a first cache bit memory between the scan input lead and the serial...
Shared memory with programmable size
A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access...
Instruction register and access port gated clock for scan cells
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for...
DC measurement method and system using sigma-delta modulation pattern
Disclosed are methods, systems, and algorithms for accurately measuring a DC voltage signal (V.sub.in) using a sigma-delta modulator (36). The preferred...
Method of and apparatus for implementing adaptive downstream modulation in
a fixed wireless communication system
Available quadrature amplitude modulation ("QAM") carriers transmittable by a base station to customer sites are substantially equally divided among the sites...
Turbo decoder stopping criterion improvement
A stopping criterion improvement for a turbo decoder that does not require division by a variable quantity. The stopping criterion improved upon generates a...
Dual mask capacitor for integrated circuits
An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor...
Pulse width modulation sequence generation
An electronic method for addressing and synchronizing a spatial light modulator (SLM) device when used with color scrolling recovery (SCR) illumination. This...
DMD pixel with small-rotated-moved via2 to reduce beam-electrode shorts
A digital micromirror device with an optimized beam dimple formed over the via2 to provide process margin by increasing the clearance between the beam and the...
All-analog calibration of sting-DAC linearity: application to high voltage
A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of...
Method and circuit for overload recovery of an amplifier
A method and circuit for providing a faster overload recovery time for an amplifier circuit is provided. An overload recovery circuit is configured to reduce...
Method and structure for improving the linearity of MOS switches
A technique is provided to linearize a MOS switch on-resistance and the nonlinear junction capacitance. The technique linearizes the sampling switch by using a...
Circuitry for reducing the skew between two signals
An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block...
Time division multiplexed serial bus with increased bandwidth
The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to...
Parallel integrated circuit test apparatus and test method
A test apparatus (400) comprising a single handler (404) is coupled to a first tester (436) and second tester (408), wherein the first (436) and second (408)...
Low drop-out voltage regulator with power supply rejection boost circuit
A low drop-out voltage regulator uses a voltage subtractor circuit 36 to form a power supply rejection boost circuit. The voltage subtractor 36 is inserted...
Flash memory array structure and method of forming
A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the...
An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the ...
Single poly EEPROM with improved coupling ratio
A semiconductor device (200) comprising a semiconductor substrate (210) having a well (220) located therein and a first dielectric (250) located over the well...
Method of forming metal oxide gate structures and capacitor electrodes
An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method...