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Patent # Description
US-6,927,933 Apparatus configured for applying write signals for driving a write head and method for configuring
An apparatus configured according to characteristics for driving a write head to write to a memory device includes: (a) a current directing circuit directing a...
US-6,927,719 Segmented, current-mode digital-to-analog converter
A segmented current mode DAC (200) is disclosed herein having a current matching circuit (260) that compensates for the current mismatch produced by the...
US-6,927,632 Low distortion compression amplifier
A low distortion compression amplifier comprising an amplifier circuit having an input and an output, wherein an input signal is received at the input and...
US-6,927,624 Method and circuit for improving control of trimming procedure
A method and circuit is provided for improving the control of the trimming procedure for various devices without the need for additional dedicated control pins....
US-6,927,493 Sealing and protecting integrated circuit bonding pads
A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and...
US-6,927,428 Lateral heterojunction bipolar transistor
A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20),...
US-6,927,174 Site-specific method for large area uniform thickness plan view transmission electron microscopy sample preparation
A method for preparing a sample includes separating a portion of substrate from a sample, performing focused ion beam milling, and removing additional sample...
US-6,927,159 Methods for providing improved layer adhesion in a semiconductor device
According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a...
US-6,927,137 Forming a retrograde well in a transistor to enhance performance of the transistor
A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the...
US-6,927,106 Methods for fabricating a triple-gate MOSFET transistor
Fabrication methods are presented in which a semiconductor body is deposited in a cavity of a temporary form structure above a semiconductor starting structure....
US-6,927,081 Method of inkless wafer blind assembly
A method of blind assembly processing a wafer by pick and place equipment is described. This method includes determining the wafer diameter or radius and...
US-6,926,150 Protective interleaf for stacked wafer shipping
A package includes a first and a second wafer stored therein in a stacked configuration. The first wafer has interconnection conductor material portions...
US-6,925,634 Method for maintaining cache coherency in software in a shared memory system
The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software...
US-6,925,521 Scheme for implementing breakpoints for on-chip ROM code patching
The present invention relates to a system and a method for preventing address conflicts when establishing breakpoints and applying one or more patches to code...
US-6,925,408 Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components
A mixed-signal core designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby,...
US-6,925,171 Universal impedance matching network for the subscriber line integrated circuits
A codifier/decodifier (CODEC) filter circuit (250) connected in a subscriber line interface circuit (202) includes a transmit section (264, 262, 260) for...
US-6,925,025 SRAM device and a method of powering-down the same
An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array, (2) peripheral circuitry coupled to...
US-6,925,010 Static random access memory device having decreased sensitivity to variations in channel physical characteristics
A static random access memory (SRAM) device and a method of manufacturing the same. In one embodiment, the SRAM device includes: (1) a first bias voltage contact...
US-6,924,756 Method and system for processing a digital signal
Processing signals to record media information includes receiving an analog signal at an analog-to-digital converter, where the analog signal includes media...
US-6,924,681 Efficient pulse amplitude modulation transmit modulation
Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408...
US-6,924,672 CMOS comparator output stage and method
A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first...
US-6,924,633 Pulse width modulation controller with double pulse immunity
A pulse width modulation (PWM) controller includes a shutter circuit interposed between a PWM modulator and a driver circuit. The shutter circuit receives a raw...
US-6,924,239 Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using "spike"...
The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein...
US-6,924,208 Dual mask capacitor for integrated circuits
An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor...
US-6,922,829 Method of generating profile-optimized code
A method of generating profiled optimized code using user interface (17) that allows a user to visually understand, inspect, and manipulate a compiled...
US-6,922,735 Management of co-processor information by integrating non-program information with program information
A system including a host processor (11) operating in combination with one or more co-processors (13) is disclosed. In this system, a file storage facility (17)...
US-6,922,710 Hand-held calculator with problems and operations linked lists
A hand-held calculator programmed to teach mathematics in a manner which emulates traditional step-by-step teacher-student teaching methods and shows the...
US-6,922,483 Methods for measuring DMD low frequency spatial uniformity
Methods for measuring the low spatial reflectivity uniformity of a DMD spatial light modulator. These methods are unique since they compensate for the...
US-6,922,470 Hybrid DC-feed controller for a subscriber line interface circuit
A method and apparatus in a DC-feed controller for controlling a subscriber line interface circuit controlling voltage (alternately, current) on a telephone line...
US-6,922,448 Upstream power back-off
The present invention provides a system and method of an upstream power back-off in a very high rate Digital Subscriber Line (VDSL) system. The method is based...
US-6,922,407 HomePNA 10M8 compliant transceiver
The present invention provides a method and system of transceiving a data signal in a HomePNA type network. The transceiver enables digital signal processing of...
US-6,922,370 High performance SRAM device and method of powering-down the same
An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage...
US-6,922,346 System and method to limit maximum duty cycle and/or provide a maximum volt-second clamp
A system and method are disclosed to limit a maximum duty cycle and/or provide a volt-second clamp for a pulse-width modulated (PWM) signal. Depending on the...
US-6,922,235 Detecting a defect of an integrated circuit
Detecting a defect of an integrated circuit includes illuminating an integrated circuit with an optical beam. The integrated circuit includes a substrate, a...
US-6,922,165 Method and circuit for gain and/or offset correction in a capacitor digital-to-analog converter
A method and circuit for gain and/or offset correction in a CDAC circuit are provided. The gain and/or offset correction can be realized by adjusting the...
US-6,922,048 Integrated circuit leadframes patterned for measuring the accurate amplitude of changing currents
A metallic leadframe for use with a semiconductor chip intended for operation in a changing magnetic field comprises a chip mount pad having at least one slit...
US-6,922,039 Dynamic control timer circuit and method
The present invention comprises a circuit and method for controlling current to a load. In an exemplary embodiment, the circuit makes the maximum charge time...
US-6,921,962 Integrated circuit having a thin film resistor located within a multilevel dielectric between an upper and...
A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through...
US-6,921,721 Post plasma clean process for a hardmask
The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes...
US-6,921,703 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-6,921,701 Method of manufacturing and structure of semiconductor device (DEMOS) with field oxide structure
A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of...
US-6,921,680 Method and apparatus for MEMS device nebulizer lubrication system
A nebulization system, which creates a uniform fog of tiny suspended liquid droplets, to lubricate the surfaces of MEMS devices. These droplets fall over the...
US-6,920,572 Unanimous voting for disabling of shared component clocking in a multicore DSP device
A digital signal processing chip having a multiple processor cores with corresponding processor subsystems, a shared component, and a clock tree, is disclosed...
US-6,920,471 Compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss
A simple, power efficient and inexpensive digital compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss. The...
US-6,920,416 Electronic systems testing employing embedded serial scan generator
An electronic system includes electronic circuitry to be tested having serial scan shift register latches, and a serial scan generator embedded in the electronic...
US-6,920,220 Pre-zero crossing signal generator for sinusoidal voltages with DC offsets such as telephone ring voltages
A circuit for closing a relay when an active AC voltage connected to one of the contacts of the relay is approximately zero volts includes a monitoring circuit...
US-6,920,193 Wireless receiver using noise levels for combining signals having spatial diversity
A wireless receiver for receiving an incoming signal having spatial and temporal diversity. The receiver uses noise-based prescaling of multiple receiver chain...
US-6,919,870 Driving circuit
The objective of this invention is to compensate or avoid the influence of offset in an easy and efficient manner, to correctly match the voltage of the output...
US-6,919,753 Temperature independent CMOS reference voltage circuit for low-voltage applications
A temperature independent CMOS reference voltage circuit includes a CMOS current mirror circuit containing first and second CMOS transistors of a first polarity....
US-6,919,751 Dynamic receiver clamp that is enabled during periods in which overshoot is likely
A dynamic clamp 200 selectively clamps overshoot on a signal line 100 when overshoot is likely, while not clamping the received signal at times when overshoot is...
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