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Patent # Description
US-9,349,933 Vertical thermoelectric structures
A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive...
US-9,348,558 Processor with efficient arithmetic units
A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of...
US-9,348,349 Control for voltage regulators
A mixed signal approach is applied to detect an output voltage condition as applied to a load. A current mode monitoring approach can be adopted and applied in...
US-9,348,345 Fixed frequency DC to DC converter control circuit with improved load transient response
Analog pulse width modulation (PWM) control circuits and techniques are presented for improving output voltage load transient response in controlling DC to DC...
US-9,348,136 Micromirror apparatus and methods
A DMD having an array of micromirror pixels wherein each pixel comprises a right electrode on a first side of the pixel, a left electrode on a second side of...
US-9,347,994 Boundary scan with coarse and fine delay register clock circuitry
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits...
US-9,347,992 IC and core taps with input and linking module circuitry
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for...
US-9,347,991 Scan throughput enhancement in scan testing of a device-under-test
Systems and methods for enabling scan testing of device-under-test (DUT) are disclosed. In an embodiment, a test system for scan testing the DUT, including P...
US-9,347,897 Characterizing dimensions of structures via scanning probe microscopy
A method comprising characterizing the dimensions of structures on a semiconductor device having dimensions less than approximately 100 nanometers (nm) using...
US-9,347,808 Flush mounted ultrasonic transducer arrays for flow measurement
A flow meter system includes a first ultrasonic transducer array to be flush-mounted to a pipe. The system also includes a second ultrasonic transducer array to...
US-9,345,088 LED control circuits and methods
An LED controller is disclosed herein. An embodiment of the controller includes a first input connectable to a power source and an output connectable to at...
US-9,344,743 Flexible region based sample adaptive offset (SAO) and adaptive loop filter (ALF)
A method for in-loop filtering in a video encoder is provided that includes determining filter parameters for each filtering region of a plurality of filtering...
US-9,344,696 Methods and apparatus for optical display using multiple spatial light modulators for increased resolution
A system for displaying a high resolution video image utilizing multiple spatial light modulators includes at least one illumination source configured to...
US-9,344,694 Spatial light modulator sub-pixel architecture and method
A semiconductor device comprises an array of individually controllable image pixels arranged in a plurality of reset groups. Each of the image pixels in the...
US-9,344,314 Computer generated sequences for downlink and uplink signals in wireless communication systems
The present disclosure provides a base station transmitter, a user equipment transmitter and methods of operating the base station and user equipment...
US-9,344,097 Fast acquisition frequency detector
A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary...
US-9,344,070 Relaxation oscillator with low drift and native offset cancellation
Relaxation oscillator circuitry is presented with low drift and native offset cancellation, including an amplifier amplifying a first current signal to provide...
US-9,344,066 Digital open loop duty cycle correction circuit
A duty cycle correction (DCC) circuit includes a master delay line that receives an input clock and determines a period of the input clock. A calibration module...
US-9,344,014 Piezoelectric device
Piezoelectric harvesting devices are disclosed herein. An embodiment of a harvesting device includes a cantilever having a resonant frequency associated...
US-9,343,962 Power regulator system with adaptive ramp signal generator
One embodiment includes a power regulator system. The system includes a switch control stage configured to generate at least one activation signal based on a...
US-9,343,949 Control circuit to detect a noise signal during a state change of a switch
Several circuits and methods for driver control of a switching circuit are disclosed. In an embodiment, a circuit for driver control of a switching circuit...
US-9,343,898 Driver current control apparatus and methods
Apparatus and methods disclosed herein implement steady-state and fast transient electronic current limiting through power transistors, including power...
US-9,343,468 Feed-forward bidirectional implanted split-gate flash memory cell
A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second...
US-9,343,459 Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect
Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions...
US-9,343,447 Optically pumped sensors or references with die-to-package cavities
An optoelectronic packaged device includes stacked components within a package including a package substrate providing side and a bottom wall. The stacked...
US-9,343,332 Alignment to multiple layers
A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a...
US-9,342,482 On-chip spectral analysis using enhanced recursive discrete Fourier transforms
A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold...
US-9,342,468 Memory time stamp register external to first and second processors
A method and system of inserting marker values used to correlate trace data as between processor cores. At least some of the illustrative embodiments are...
US-9,342,312 Processor with inter-execution unit instruction issue
A processor includes an instruction storage memory, a processor core, and an instruction merge unit. The processor core includes a plurality of execution units...
US-9,342,259 Nonvolatile logic array and power domain segmentation in processing device
A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element...
US-9,342,124 Programmable and simultaneous load switch control for power sequencing
A power delivery and control device that includes a voltage input line, a voltage output line, a control logic unit coupled to the voltage input and voltage...
US-9,342,089 Verification of bandgap reference startup
A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and...
US-9,341,658 Fast on-chip oscillator trimming
Oscillation frequency measurements for trimming oscillators on an integrated circuit device are performed entirely on the device. The oscillation frequency...
US-9,341,543 Method and OTDR apparatus for optical cable defect location with reduced memory requirement
Optical time domain reflectometer (OTDR) systems, methods and integrated circuits are presented for locating defects in an optical cable or other optical cable,...
US-9,340,415 MEMS device with non-planar features
A MEMS device is formed with facing surfaces of a contoured substrate and a layer of material having complementary contours. In one fabrication approach, a...
US-9,338,757 Clock synchronization and centralized guard time provisioning
Embodiments of the invention provide a method to accommodate clock drift and guard time in a centralized fashion. In one embodiment, a first device is adapted...
US-9,338,533 Drivers and methods of driving transducers
A transducer has an input and produces a mechanical output, wherein the magnitude of the mechanical output of the transducer is dependent on the frequency and...
US-9,337,905 Inductive structures with reduced emissions and interference
An inductive structure includes a power coil and a data coil. The data coil is substantially centered within the power coil. A first portion of the data coil...
US-9,337,789 Differential receiver
A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential...
US-9,337,780 Amplifier with sample and hold output and low drive stage
An amplifier (50) for voice or audio signals, and particularly for headset applications, uses a low g.sub.m amplifier (54) for initially charging an output node...
US-9,337,738 Transformer-coupled gate-drive power regulator system
A transformer-coupled gate-drive power regulator system is provided that includes a feedback stage that generates a PWM signal having a duty-cycle that is based...
US-9,337,653 Static MEMS switch for ESD protection
An integrated circuit with either a normally open MEMS ESD protection switch coupled between a bond pad and an internal circuit or a normally closed MEMS ESD...
US-9,337,330 Scheme to align LDMOS drain extension to moat
An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a...
US-9,337,299 Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate
A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p-...
US-9,337,297 Fringe capacitance reduction for replacement gate CMOS
A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls...
US-9,337,292 Very high aspect ratio contact
A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the...
US-9,337,130 Leadframe strip and leadframes
A leadframe strip including a first leadframe having a first die pad and a first plurality of generally parallel leads each extending outwardly relative to the...
US-9,337,106 Implant profiling with resist
A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist...
US-9,337,046 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
US-9,337,044 System and method for mitigating oxide growth in a gate dielectric
Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in...
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